Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c434037e authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "power: supply: qpnp-qnovo5: Fix parameter configurations"

parents 22370f2a 2fedd00d
Loading
Loading
Loading
Loading
+3 −0
Original line number Diff line number Diff line
@@ -447,6 +447,9 @@ static struct device_attribute power_supply_attrs[] = {
	POWER_SUPPLY_ATTR(toggle_stat),
	POWER_SUPPLY_ATTR(main_fcc_max),
	POWER_SUPPLY_ATTR(fg_reset),
	POWER_SUPPLY_ATTR(qc_opti_disable),
	POWER_SUPPLY_ATTR(cc_soc),
	POWER_SUPPLY_ATTR(batt_age_level),
	/* Charge pump properties */
	POWER_SUPPLY_ATTR(cp_status1),
	POWER_SUPPLY_ATTR(cp_status2),
+27 −1
Original line number Diff line number Diff line
@@ -220,6 +220,19 @@ static int pt_dis_votable_cb(struct votable *votable, void *data, int disable,
{
	struct qnovo *chip = data;
	int rc;
	u8 val = 0;

	if (!disable) {
		rc = qnovo5_write(chip, QNOVO_PHASE, &val, 1);
		if (rc < 0)
			dev_err(chip->dev, "Couldn't write to QNOVO_PHASE rc=%d\n",
				rc);

		rc = qnovo5_write(chip, QNOVO_P2_TICK, &val, 1);
		if (rc < 0)
			dev_err(chip->dev, "Couldn't write to QNOVO_P2_TICK rc=%d\n",
				rc);
	}

	rc = qnovo5_masked_write(chip, QNOVO_PE_CTRL, QNOVO_PTRAIN_EN_BIT,
				 (bool)disable ? 0 : QNOVO_PTRAIN_EN_BIT);
@@ -298,6 +311,7 @@ enum {
	PE_CTRL_REG,
	PTRAIN_STS_REG,
	ERR_STS_REG,
	ERROR_MASK_REG,
	PREST1,
	NREST1,
	NPULS1,
@@ -364,6 +378,12 @@ static struct param_info params[] = {
		.num_regs		= 1,
		.units_str		= "",
	},
	[ERROR_MASK_REG] = {
		.name			= "ERROR_MASK",
		.start_addr		= QNOVO_ERROR_MASK,
		.num_regs		= 1,
		.units_str		= "",
	},
	[PREST1] = {
		.name			= "PREST1",
		.start_addr		= QNOVO_PREST1_CTRL,
@@ -454,6 +474,8 @@ static struct param_info params[] = {
		.num_regs		= 2,
		.reg_to_unit_multiplier	= 305185, /* converts to nA */
		.reg_to_unit_divider	= 1,
		.min_val		= -10000000,
		.max_val		= 10000000,
		.units_str		= "uA",
	},
	[PTTIME] = {
@@ -470,6 +492,8 @@ static struct param_info params[] = {
		.num_regs		= 2,
		.reg_to_unit_multiplier	= 1,
		.reg_to_unit_divider	= 1,
		.min_val		= 0,
		.max_val		= 65535,
		.units_str		= "S",
	},
	[NREST2] = {
@@ -868,7 +892,7 @@ static ssize_t current_store(struct class *c, struct class_attribute *attr,
	if (i < 0)
		return -EINVAL;

	if (kstrtoul(ubuf, 0, &val_uA))
	if (kstrtol(ubuf, 0, &val_uA))
		return -EINVAL;

	if (val_uA < params[i].min_val || val_uA > params[i].max_val) {
@@ -991,6 +1015,7 @@ CLASS_ATTR_IDX_RW(fcc_uA_request, val);
CLASS_ATTR_IDX_RW(PE_CTRL_REG, reg);
CLASS_ATTR_IDX_RO(PTRAIN_STS_REG, reg);
CLASS_ATTR_IDX_RO(ERR_STS_REG, reg);
CLASS_ATTR_IDX_RW(ERROR_MASK, reg);
CLASS_ATTR_IDX_RW(PREST1_uS, time);
CLASS_ATTR_IDX_RW(NREST1_uS, time);
CLASS_ATTR_IDX_RW(NPULS1_uS, time);
@@ -1028,6 +1053,7 @@ static struct attribute *qnovo_class_attrs[] = {
	[PE_CTRL_REG]		= &class_attr_PE_CTRL_REG.attr,
	[PTRAIN_STS_REG]	= &class_attr_PTRAIN_STS_REG.attr,
	[ERR_STS_REG]		= &class_attr_ERR_STS_REG.attr,
	[ERROR_MASK_REG]	= &class_attr_ERROR_MASK.attr,
	[PREST1]		= &class_attr_PREST1_uS.attr,
	[NREST1]		= &class_attr_NREST1_uS.attr,
	[NPULS1]		= &class_attr_NPULS1_uS.attr,
+9 −0
Original line number Diff line number Diff line
@@ -145,6 +145,12 @@ enum {
	POWER_SUPPLY_PD_PPS_ACTIVE,
};

enum {
	POWER_SUPPLY_QC_CTM_DISABLE = BIT(0),
	POWER_SUPPLY_QC_THERMAL_BALANCE_DISABLE = BIT(1),
	POWER_SUPPLY_QC_INOV_THERMAL_DISABLE = BIT(2),
};

enum power_supply_property {
	/* Properties of type `int' */
	POWER_SUPPLY_PROP_STATUS = 0,
@@ -314,6 +320,9 @@ enum power_supply_property {
	POWER_SUPPLY_PROP_TOGGLE_STAT,
	POWER_SUPPLY_PROP_MAIN_FCC_MAX,
	POWER_SUPPLY_PROP_FG_RESET,
	POWER_SUPPLY_PROP_QC_OPTI_DISABLE,
	POWER_SUPPLY_PROP_CC_SOC,
	POWER_SUPPLY_PROP_BATT_AGE_LEVEL,
	/* Charge pump properties */
	POWER_SUPPLY_PROP_CP_STATUS1,
	POWER_SUPPLY_PROP_CP_STATUS2,