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Commit c4270d12 authored by Changbin Du's avatar Changbin Du Committed by Zhenyu Wang
Browse files

drm/i915/gvt: Emulate PCI expansion ROM base address register 



Our vGPU doesn't have a device ROM, we need follow the PCI spec to
report this info to drivers. Otherwise, we would see below errors.

Inspecting possible rom at 0xfe049000 (vd=8086:1912 bdf=00:10.0)
qemu-system-x86_64: vfio-pci: Cannot read device rom at 00000000-0000-0000-0000-000000000001
Device option ROM contents are probably invalid (check dmesg).
Skip option ROM probe with rombar=0, or load from file with romfile=No option rom signature (got 4860)

I will also send a improvement patch to PCI subsystem related to PCI ROM.
But no idea to omit below error, since no pattern to detect vbios shadow
without touch its content.
0000:00:10.0: Invalid PCI ROM header signature: expecting 0xaa55, got 0x0000

Signed-off-by: default avatarChangbin Du <changbin.du@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent c982c45d

drivers/gpu/drm/i915/gvt/cfg_space.c

+21 −0
Original line number Diff line number Diff line
@@ -208,6 +208,20 @@ static int emulate_pci_command_write(struct intel_vgpu *vgpu, 
	return 0;

}



static int emulate_pci_rom_bar_write(struct intel_vgpu *vgpu,

	unsigned int offset, void *p_data, unsigned int bytes)

{

	u32 *pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);

	u32 new = *(u32 *)(p_data);



	if ((new & PCI_ROM_ADDRESS_MASK) == PCI_ROM_ADDRESS_MASK)

		/* We don't have rom, return size of 0. */

		*pval = 0;

	else

		vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);

	return 0;

}



static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,

	void *p_data, unsigned int bytes)

{
@@ -300,6 +314,11 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 
	}



	switch (rounddown(offset, 4)) {

	case PCI_ROM_ADDRESS:

		if (WARN_ON(!IS_ALIGNED(offset, 4)))

			return -EINVAL;

		return emulate_pci_rom_bar_write(vgpu, offset, p_data, bytes);



	case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5:

		if (WARN_ON(!IS_ALIGNED(offset, 4)))

			return -EINVAL;
@@ -375,6 +394,8 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, 
				pci_resource_len(gvt->dev_priv->drm.pdev, 0);

	vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size =

				pci_resource_len(gvt->dev_priv->drm.pdev, 2);



	memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4);

}



/**