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Commit c3d68d8d authored by Hongbo Zhang's avatar Hongbo Zhang Committed by Vinod Koul
Browse files

DMA: Freescale: revise device tree binding document 



This patch updates the discription of each type of DMA controller and its
channels, it is preparation for adding another new DMA controller binding, it
also fixes some defects of indent for text alignment at the same time.

Signed-off-by: default avatarHongbo Zhang <hongbo.zhang@freescale.com>
Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
parent c3cc74b2

Documentation/devicetree/bindings/powerpc/fsl/dma.txt

+31 −37
Original line number Diff line number Diff line 
* Freescale 83xx DMA Controller

* Freescale DMA Controllers



Freescale PowerPC 83xx have on chip general purpose DMA controllers.

** Freescale Elo DMA Controller

   This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx

   series chips such as mpc8315, mpc8349, mpc8379 etc.



Required properties:



- compatible        : compatible list, contains 2 entries, first is

		 "fsl,CHIP-dma", where CHIP is the processor

		 (mpc8349, mpc8360, etc.) and the second is

		 "fsl,elo-dma"

- reg               : <registers mapping for DMA general status reg>

- ranges		: Should be defined as specified in 1) to describe the

		  DMA controller channels.

- compatible        : must include "fsl,elo-dma"

- reg               : DMA General Status Register, i.e. DGSR which contains

                      status for all the 4 DMA channels

- ranges            : describes the mapping between the address space of the

                      DMA channels and the address space of the DMA controller

- cell-index        : controller index.  0 for controller @ 0x8100

- interrupts        : <interrupt mapping for DMA IRQ>

- interrupts        : interrupt specifier for DMA IRQ

- interrupt-parent  : optional, if needed for interrupt mapping





- DMA channel nodes:

        - compatible        : compatible list, contains 2 entries, first is

			 "fsl,CHIP-dma-channel", where CHIP is the processor

			 (mpc8349, mpc8350, etc.) and the second is

			 "fsl,elo-dma-channel". However, see note below.

        - reg               : <registers mapping for channel>

        - cell-index        : dma channel index starts at 0.

        - compatible        : must include "fsl,elo-dma-channel"

                              However, see note below.

        - reg               : DMA channel specific registers

        - cell-index        : DMA channel index starts at 0.



Optional properties:

        - interrupts        : <interrupt mapping for DMA channel IRQ>

        - interrupts        : interrupt specifier for DMA channel IRQ

                              (on 83xx this is expected to be identical to

                              the interrupts property of the parent node)

        - interrupt-parent  : optional, if needed for interrupt mapping
@@ -70,30 +67,27 @@ Example: 
		};

	};



* Freescale 85xx/86xx DMA Controller



Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers.

** Freescale EloPlus DMA Controller

   This is a 4-channel DMA controller with extended addresses and chaining,

   mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as

   mpc8540, mpc8641 p4080, bsc9131 etc.



Required properties:



- compatible        : compatible list, contains 2 entries, first is

		 "fsl,CHIP-dma", where CHIP is the processor

		 (mpc8540, mpc8540, etc.) and the second is

		 "fsl,eloplus-dma"

- reg               : <registers mapping for DMA general status reg>

- compatible        : must include "fsl,eloplus-dma"

- reg               : DMA General Status Register, i.e. DGSR which contains

                      status for all the 4 DMA channels

- cell-index        : controller index.  0 for controller @ 0x21000,

                                         1 for controller @ 0xc000

- ranges		: Should be defined as specified in 1) to describe the

		  DMA controller channels.

- ranges            : describes the mapping between the address space of the

                      DMA channels and the address space of the DMA controller



- DMA channel nodes:

        - compatible        : compatible list, contains 2 entries, first is

			 "fsl,CHIP-dma-channel", where CHIP is the processor

			 (mpc8540, mpc8560, etc.) and the second is

			 "fsl,eloplus-dma-channel". However, see note below.

        - cell-index        : dma channel index starts at 0.

        - reg               : <registers mapping for channel>

        - interrupts        : <interrupt mapping for DMA channel IRQ>

        - compatible        : must include "fsl,eloplus-dma-channel"

                              However, see note below.

        - cell-index        : DMA channel index starts at 0.

        - reg               : DMA channel specific registers

        - interrupts        : interrupt specifier for DMA channel IRQ

        - interrupt-parent  : optional, if needed for interrupt mapping



Example: