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Commit c39378fc authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull pin control fixes from Linus Walleij:
 "Here are a few pin control fixes for the v4.8 series, nothing special
  about them:

   - Add the missing <linux/io.h> header to the Intel Merrifield driver
     to get rid of build mess.

   - Drop two instances of pinctrl_unregister() called for drivers using
     devm_* resource management.

   - Remove the default debounce time for the AMD driver"

* tag 'pinctrl-v4.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: intel: merrifield: Add missed header
  pinctrl/amd: Remove the default de-bounce time
  pinctrl: pistachio: Drop pinctrl_unregister for devm_ registered device
  pinctrl: meson: Drop pinctrl_unregister for devm_ registered device
parents 3684b03d e95d0dfb
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+1 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@

#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinconf.h>
+1 −7
Original line number Diff line number Diff line
@@ -727,13 +727,7 @@ static int meson_pinctrl_probe(struct platform_device *pdev)
		return PTR_ERR(pc->pcdev);
	}

	ret = meson_gpiolib_register(pc);
	if (ret) {
		pinctrl_unregister(pc->pcdev);
		return ret;
	}

	return 0;
	return meson_gpiolib_register(pc);
}

static struct platform_driver meson_pinctrl_driver = {
+0 −20
Original line number Diff line number Diff line
@@ -43,17 +43,6 @@ static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)

	spin_lock_irqsave(&gpio_dev->lock, flags);
	pin_reg = readl(gpio_dev->base + offset * 4);
	/*
	 * Suppose BIOS or Bootloader sets specific debounce for the
	 * GPIO. if not, set debounce to be  2.75ms and remove glitch.
	*/
	if ((pin_reg & DB_TMR_OUT_MASK) == 0) {
		pin_reg |= 0xf;
		pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
		pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
	}

	pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
	writel(pin_reg, gpio_dev->base + offset * 4);
	spin_unlock_irqrestore(&gpio_dev->lock, flags);
@@ -326,15 +315,6 @@ static void amd_gpio_irq_enable(struct irq_data *d)

	spin_lock_irqsave(&gpio_dev->lock, flags);
	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
	/*
		Suppose BIOS or Bootloader sets specific debounce for the
		GPIO. if not, set debounce to be  2.75ms.
	*/
	if ((pin_reg & DB_TMR_OUT_MASK) == 0) {
		pin_reg |= 0xf;
		pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
		pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
	}
	pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
	pin_reg |= BIT(INTERRUPT_MASK_OFF);
	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+1 −8
Original line number Diff line number Diff line
@@ -1432,7 +1432,6 @@ static int pistachio_pinctrl_probe(struct platform_device *pdev)
{
	struct pistachio_pinctrl *pctl;
	struct resource *res;
	int ret;

	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
	if (!pctl)
@@ -1464,13 +1463,7 @@ static int pistachio_pinctrl_probe(struct platform_device *pdev)
		return PTR_ERR(pctl->pctldev);
	}

	ret = pistachio_gpio_register(pctl);
	if (ret < 0) {
		pinctrl_unregister(pctl->pctldev);
		return ret;
	}

	return 0;
	return pistachio_gpio_register(pctl);
}

static struct platform_driver pistachio_pinctrl_driver = {