Loading drivers/gpu/msm/adreno_a6xx.c +9 −4 Original line number Original line Diff line number Diff line Loading @@ -384,9 +384,6 @@ static const struct kgsl_hwcg_reg a612_hwcg_regs[] = { {A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, {A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, {A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, {A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, {A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, {A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, {A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, {A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, {A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, {A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, {A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, {A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, {A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, {A6XX_RBBM_ISDB_CNT, 0x00000182}, {A6XX_RBBM_ISDB_CNT, 0x00000182}, Loading Loading @@ -1155,6 +1152,7 @@ static void _set_ordinals(struct adreno_device *adreno_dev, static int a6xx_send_cp_init(struct adreno_device *adreno_dev, static int a6xx_send_cp_init(struct adreno_device *adreno_dev, struct adreno_ringbuffer *rb) struct adreno_ringbuffer *rb) { { struct kgsl_device *device = KGSL_DEVICE(adreno_dev); unsigned int *cmds; unsigned int *cmds; int ret; int ret; Loading @@ -1167,10 +1165,17 @@ static int a6xx_send_cp_init(struct adreno_device *adreno_dev, _set_ordinals(adreno_dev, cmds, 11); _set_ordinals(adreno_dev, cmds, 11); ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000); ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000); if (ret) if (ret) { adreno_spin_idle_debug(adreno_dev, adreno_spin_idle_debug(adreno_dev, "CP initialization failed to idle\n"); "CP initialization failed to idle\n"); if (!adreno_is_a3xx(adreno_dev)) kgsl_sharedmem_writel(device, &device->scratch, SCRATCH_RPTR_OFFSET(rb->id), 0); rb->wptr = 0; rb->_wptr = 0; } return ret; return ret; } } Loading Loading
drivers/gpu/msm/adreno_a6xx.c +9 −4 Original line number Original line Diff line number Diff line Loading @@ -384,9 +384,6 @@ static const struct kgsl_hwcg_reg a612_hwcg_regs[] = { {A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, {A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, {A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, {A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, {A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, {A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, {A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, {A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, {A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, {A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, {A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, {A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, {A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, {A6XX_RBBM_ISDB_CNT, 0x00000182}, {A6XX_RBBM_ISDB_CNT, 0x00000182}, Loading Loading @@ -1155,6 +1152,7 @@ static void _set_ordinals(struct adreno_device *adreno_dev, static int a6xx_send_cp_init(struct adreno_device *adreno_dev, static int a6xx_send_cp_init(struct adreno_device *adreno_dev, struct adreno_ringbuffer *rb) struct adreno_ringbuffer *rb) { { struct kgsl_device *device = KGSL_DEVICE(adreno_dev); unsigned int *cmds; unsigned int *cmds; int ret; int ret; Loading @@ -1167,10 +1165,17 @@ static int a6xx_send_cp_init(struct adreno_device *adreno_dev, _set_ordinals(adreno_dev, cmds, 11); _set_ordinals(adreno_dev, cmds, 11); ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000); ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000); if (ret) if (ret) { adreno_spin_idle_debug(adreno_dev, adreno_spin_idle_debug(adreno_dev, "CP initialization failed to idle\n"); "CP initialization failed to idle\n"); if (!adreno_is_a3xx(adreno_dev)) kgsl_sharedmem_writel(device, &device->scratch, SCRATCH_RPTR_OFFSET(rb->id), 0); rb->wptr = 0; rb->_wptr = 0; } return ret; return ret; } } Loading