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Commit c382babc authored by Azhar Shaikh's avatar Azhar Shaikh Committed by Jarkko Sakkinen
Browse files

tpm_tis: Move ilb_base_addr to tpm_tis_data



Move static variable ilb_base_addr to tpm_tis_data.

Cc: stable@vger.kernel.org
Signed-off-by: default avatarAzhar Shaikh <azhar.shaikh@intel.com>
Reviewed-by: default avatarJarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
Tested-by: default avatarJarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
Signed-off-by: default avatarJarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
parent 0b66f2a0
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+28 −47
Original line number Diff line number Diff line
@@ -134,33 +134,24 @@ static int check_acpi_tpm2(struct device *dev)
#endif

#ifdef CONFIG_X86
#define INTEL_LEGACY_BLK_BASE_ADDR      0xFED08000
#define ILB_REMAP_SIZE			0x100
#define LPC_CNTRL_REG_OFFSET            0x84
#define LPC_CNTRL_OFFSET		0x84
#define LPC_CLKRUN_EN			(1 << 2)

static void __iomem *ilb_base_addr;

static inline bool is_bsw(void)
{
	return ((boot_cpu_data.x86_model == INTEL_FAM6_ATOM_AIRMONT) ? 1 : 0);
}

/**
 * tpm_platform_begin_xfer() - clear LPC CLKRUN_EN i.e. clocks will be running
 */
static void tpm_platform_begin_xfer(void)
static void tpm_platform_begin_xfer(struct tpm_tis_data *data)
{
	u32 clkrun_val;

	if (!is_bsw())
		return;

	clkrun_val = ioread32(ilb_base_addr + LPC_CNTRL_REG_OFFSET);
	clkrun_val = ioread32(data->ilb_base_addr + LPC_CNTRL_OFFSET);

	/* Disable LPC CLKRUN# */
	clkrun_val &= ~LPC_CLKRUN_EN;
	iowrite32(clkrun_val, ilb_base_addr + LPC_CNTRL_REG_OFFSET);
	iowrite32(clkrun_val, data->ilb_base_addr + LPC_CNTRL_OFFSET);

	/*
	 * Write any random value on port 0x80 which is on LPC, to make
@@ -173,18 +164,18 @@ static void tpm_platform_begin_xfer(void)
/**
 * tpm_platform_end_xfer() - set LPC CLKRUN_EN i.e. clocks can be turned off
 */
static void tpm_platform_end_xfer(void)
static void tpm_platform_end_xfer(struct tpm_tis_data *data)
{
	u32 clkrun_val;

	if (!is_bsw())
		return;

	clkrun_val = ioread32(ilb_base_addr + LPC_CNTRL_REG_OFFSET);
	clkrun_val = ioread32(data->ilb_base_addr + LPC_CNTRL_OFFSET);

	/* Enable LPC CLKRUN# */
	clkrun_val |= LPC_CLKRUN_EN;
	iowrite32(clkrun_val, ilb_base_addr + LPC_CNTRL_REG_OFFSET);
	iowrite32(clkrun_val, data->ilb_base_addr + LPC_CNTRL_OFFSET);

	/*
	 * Write any random value on port 0x80 which is on LPC, to make
@@ -194,16 +185,11 @@ static void tpm_platform_end_xfer(void)

}
#else
static inline bool is_bsw(void)
{
	return false;
}

static void tpm_platform_begin_xfer(void)
static void tpm_platform_begin_xfer(struct tpm_tis_data *data)
{
}

static void tpm_platform_end_xfer(void)
static void tpm_platform_end_xfer(struct tpm_tis_data *data)
{
}
#endif
@@ -213,12 +199,12 @@ static int tpm_tcg_read_bytes(struct tpm_tis_data *data, u32 addr, u16 len,
{
	struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);

	tpm_platform_begin_xfer();
	tpm_platform_begin_xfer(data);

	while (len--)
		*result++ = ioread8(phy->iobase + addr);

	tpm_platform_end_xfer();
	tpm_platform_end_xfer(data);

	return 0;
}
@@ -228,12 +214,12 @@ static int tpm_tcg_write_bytes(struct tpm_tis_data *data, u32 addr, u16 len,
{
	struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);

	tpm_platform_begin_xfer();
	tpm_platform_begin_xfer(data);

	while (len--)
		iowrite8(*value++, phy->iobase + addr);

	tpm_platform_end_xfer();
	tpm_platform_end_xfer(data);

	return 0;
}
@@ -242,11 +228,11 @@ static int tpm_tcg_read16(struct tpm_tis_data *data, u32 addr, u16 *result)
{
	struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);

	tpm_platform_begin_xfer();
	tpm_platform_begin_xfer(data);

	*result = ioread16(phy->iobase + addr);

	tpm_platform_end_xfer();
	tpm_platform_end_xfer(data);

	return 0;
}
@@ -255,11 +241,11 @@ static int tpm_tcg_read32(struct tpm_tis_data *data, u32 addr, u32 *result)
{
	struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);

	tpm_platform_begin_xfer();
	tpm_platform_begin_xfer(data);

	*result = ioread32(phy->iobase + addr);

	tpm_platform_end_xfer();
	tpm_platform_end_xfer(data);

	return 0;
}
@@ -268,11 +254,11 @@ static int tpm_tcg_write32(struct tpm_tis_data *data, u32 addr, u32 value)
{
	struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);

	tpm_platform_begin_xfer();
	tpm_platform_begin_xfer(data);

	iowrite32(value, phy->iobase + addr);

	tpm_platform_end_xfer();
	tpm_platform_end_xfer(data);

	return 0;
}
@@ -351,9 +337,13 @@ MODULE_DEVICE_TABLE(pnp, tpm_pnp_tbl);
static void tpm_tis_pnp_remove(struct pnp_dev *dev)
{
	struct tpm_chip *chip = pnp_get_drvdata(dev);
	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);

	tpm_chip_unregister(chip);
	tpm_tis_remove(chip);
	if (is_bsw())
		iounmap(priv->ilb_base_addr);

}

static struct pnp_driver tis_pnp_driver = {
@@ -400,10 +390,14 @@ static int tpm_tis_plat_probe(struct platform_device *pdev)
static int tpm_tis_plat_remove(struct platform_device *pdev)
{
	struct tpm_chip *chip = dev_get_drvdata(&pdev->dev);
	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);

	tpm_chip_unregister(chip);
	tpm_tis_remove(chip);

	if (is_bsw())
		iounmap(priv->ilb_base_addr);

	return 0;
}

@@ -461,11 +455,6 @@ static int __init init_tis(void)
	if (rc)
		goto err_force;

#ifdef CONFIG_X86
	if (is_bsw())
		ilb_base_addr = ioremap(INTEL_LEGACY_BLK_BASE_ADDR,
					ILB_REMAP_SIZE);
#endif
	rc = platform_driver_register(&tis_drv);
	if (rc)
		goto err_platform;
@@ -484,10 +473,6 @@ static int __init init_tis(void)
err_platform:
	if (force_pdev)
		platform_device_unregister(force_pdev);
#ifdef CONFIG_X86
	if (is_bsw())
		iounmap(ilb_base_addr);
#endif
err_force:
	return rc;
}
@@ -497,10 +482,6 @@ static void __exit cleanup_tis(void)
	pnp_unregister_driver(&tis_pnp_driver);
	platform_driver_unregister(&tis_drv);

#ifdef CONFIG_X86
	if (is_bsw())
		iounmap(ilb_base_addr);
#endif
	if (force_pdev)
		platform_device_unregister(force_pdev);
}
+15 −1
Original line number Diff line number Diff line
@@ -766,6 +766,13 @@ int tpm_tis_core_init(struct device *dev, struct tpm_tis_data *priv, int irq,
	priv->phy_ops = phy_ops;
	dev_set_drvdata(&chip->dev, priv);

	if (is_bsw()) {
		priv->ilb_base_addr = ioremap(INTEL_LEGACY_BLK_BASE_ADDR,
					ILB_REMAP_SIZE);
		if (!priv->ilb_base_addr)
			return -ENOMEM;
	}

	if (wait_startup(chip, 0) != 0) {
		rc = -ENODEV;
		goto out_err;
@@ -856,9 +863,16 @@ int tpm_tis_core_init(struct device *dev, struct tpm_tis_data *priv, int irq,
		}
	}

	return tpm_chip_register(chip);
	rc = tpm_chip_register(chip);
	if (rc && is_bsw())
		iounmap(priv->ilb_base_addr);

	return rc;
out_err:
	tpm_tis_remove(chip);
	if (is_bsw())
		iounmap(priv->ilb_base_addr);

	return rc;
}
EXPORT_SYMBOL_GPL(tpm_tis_core_init);
+13 −0
Original line number Diff line number Diff line
@@ -79,6 +79,9 @@ enum tis_defaults {
#define	TPM_DID_VID(l)			(0x0F00 | ((l) << 12))
#define	TPM_RID(l)			(0x0F04 | ((l) << 12))

#define INTEL_LEGACY_BLK_BASE_ADDR	0xFED08000
#define ILB_REMAP_SIZE			0x100

enum tpm_tis_flags {
	TPM_TIS_ITPM_WORKAROUND		= BIT(0),
};
@@ -89,6 +92,7 @@ struct tpm_tis_data {
	int irq;
	bool irq_tested;
	unsigned int flags;
	void __iomem *ilb_base_addr;
	wait_queue_head_t int_queue;
	wait_queue_head_t read_queue;
	const struct tpm_tis_phy_ops *phy_ops;
@@ -144,6 +148,15 @@ static inline int tpm_tis_write32(struct tpm_tis_data *data, u32 addr,
	return data->phy_ops->write32(data, addr, value);
}

static inline bool is_bsw(void)
{
#ifdef CONFIG_X86
	return ((boot_cpu_data.x86_model == INTEL_FAM6_ATOM_AIRMONT) ? 1 : 0);
#else
	return false;
#endif
}

void tpm_tis_remove(struct tpm_chip *chip);
int tpm_tis_core_init(struct device *dev, struct tpm_tis_data *priv, int irq,
		      const struct tpm_tis_phy_ops *phy_ops,