Merge "dt-bindings: Add documentation for SDM660" (c36a6a2d) · Commits · e / devices / android_kernel_fairphone_FP4

bindings/arm/msm/msm.txt

+13 −0

Original line number	Diff line number	Diff line
		@@ -77,6 +77,12 @@ SoCs:
		- SDMMAGPIE
		compatible = "qcom,sdmmagpie"

		- SDM660
		compatible = "qcom,sdm660"

		- SDA660
		compatible = "qcom,sda660"

		Generic board variants:

		- CDP device:
		@@ -213,3 +219,10 @@ compatible = "qcom,sdxprairie-cdp"
		compatible = "qcom,sdmmagpie-rumi"
		compatible = "qcom,sdmmagpie-idp"
		compatible = "qcom,sdmmagpie-qrd"
		compatible = "qcom,sdm660-cdp"
		compatible = "qcom,sdm660-mtp"
		compatible = "qcom,sdm660-qrd"
		compatible = "qcom,sdm660-sim"
		compatible = "qcom,sda660-mtp"
		compatible = "qcom,sda660-cdp"
		compatible = "qcom,sda660-qrd"

bindings/arm/msm/qcom,osm-sdm660.txt

0 → 100644

+488 −0

Original line number	Diff line number	Diff line
		Qualcomm Technologies, Inc. OSM Bindings

		Operating State Manager (OSM) is a hardware engine used by some
		Qualcomm Technologies, Inc. (QTI) SoCs to manage frequency and voltage scaling
		in hardware. OSM is capable of controlling frequency and voltage requests
		for multiple clusters via the existence of multiple OSM domains.

		Properties:
		- compatible
		Usage: required
		Value type: <string>
		Definition: must be "qcom,clk-cpu-osm" or
		"qcom,clk-cpu-osm-sdm630".

		- reg
		Usage: required
		Value type: <prop-encoded-array>
		Definition: Addresses and sizes for the memory of the OSM controller,
		cluster PLL management, and APCS common register regions.
		Optionally, the address of the efuse registers used to
		determine the pwrcl or perfcl speed-bins and/or the ACD
		register space to initialize prior to enabling OSM.

		- reg-names
		Usage: required
		Value type: <stringlist>
		Definition: Address names. Must be "osm", "pwrcl_pll", "perfcl_pll",
		"apcs_common", and "debug". Optionally, "pwrcl_efuse",
		"perfcl_efuse", "pwrcl_acd", or "perfcl_acd".
		Must be specified in the same order as the corresponding
		addresses are specified in the reg property.

		- vdd-pwrcl-supply
		Usage: required
		Value type: <phandle>
		Definition: phandle of the underlying regulator device that manages
		the voltage supply of the Power cluster.

		- vdd-perfcl-supply
		Usage: required
		Value type: <phandle>
		Definition: phandle of the underlying regulator device that manages
		the voltage supply of the Performance cluster.

		- interrupts
		Usage: required
		Value type: <prop-encoded-array>
		Definition: OSM interrupt specifier.

		- interrupt-names
		Usage: required
		Value type: <stringlist>
		Definition: Interrupt names. this list must match up 1-to-1 with the
		interrupts specified in the 'interrupts' property.
		"pwrcl-irq" and "perfcl-irq" must be specified.

		- qcom,pwrcl-speedbinX-v0
		Usage: required
		Value type: <prop-encoded-array>
		Definition: Array which defines the frequency in Hertz, frequency,
		PLL override data, ACC level, and virtual corner used
		by the OSM hardware for each supported DCVS setpoint
		of the Power cluster.

		- qcom,perfcl-speedbinX-v0
		Usage: required
		Value type: <prop-encoded-array>
		Definition: Array which defines the frequency in Hertz, frequency,
		PLL override data, ACC level and virtual corner used
		by the OSM hardware for each supported DCVS setpoint
		of the Performance cluster.

		- qcom,osm-no-tz
		Usage: optional
		Value type: <empty>
		Definition: Boolean flag which indicates that there is no programming
		of the OSM hardware performed by the secure world.

		- qcom,osm-pll-setup
		Usage: optional
		Value type: <empty>
		Definition: Boolean flag which indicates that the PLL setup sequence
		must be executed for each clock domain managed by the OSM
		controller.

		- qcom,up-timer
		Usage: optional
		Value type: <prop-encoded-array>
		Definition: Array which defines the DCVS up timer value in nanoseconds
		for each of the two clusters managed by the OSM controller.

		- qcom,down-timer
		Usage: optional
		Value type: <prop-encoded-array>
		Definition: Array which defines the DCVS down timer value in nanoseconds
		for each of the two clusters managed by the OSM controller.

		- qcom,pc-override-index
		Usage: optional
		Value type: <prop-encoded-array>
		Definition: Array which defines the OSM performance index to be used
		when each cluster enters certain low power modes.

		- qcom,set-ret-inactive
		Usage: optional
		Value type: <empty>
		Definition: Boolean flag which indicates if domains in retention must
		be treated as inactive.

		- qcom,enable-llm-freq-vote
		Usage: optional
		Value type: <empty>
		Definition: Boolean flag which indicates if Limits hardware frequency
		votes must be honored by OSM.

		- qcom,llm-freq-up-timer
		Usage: optional
		Value type: <prop-encoded-array>
		Definition: Array which defines the LLM frequency up timer value in
		nanoseconds for each of the two clusters managed by the
		OSM controller.

		- qcom,llm-freq-down-timer
		Usage: optional
		Value type: <prop-encoded-array>
		Definition: Array which defines the LLM frequency down timer value in
		nanoseconds for each of the two clusters managed by the
		OSM controller.

		- qcom,enable-llm-volt-vote
		Usage: optional
		Value type: <empty>
		Definition: Boolean flag which indicates if Limits hardware voltage
		votes must be honored by OSM.

		- qcom,llm-volt-up-timer
		Usage: optional
		Value type: <prop-encoded-array>
		Definition: Array which defines the LLM voltage up timer value in
		nanoseconds for each of the two clusters managed by the
		OSM controller.

		- qcom,llm-volt-down-timer
		Usage: optional
		Value type: <prop-encoded-array>
		Definition: Array which defines the LLM voltage down timer value in
		nanoseconds for each of the two clusters managed by the
		OSM controller.

		- qcom,cc-reads
		Usage: optional
		Value type: <integer>
		Definition: Defines the number of times the cycle counters must be
		read to determine the performance level of each clock
		domain.

		- qcom,l-val-base
		Usage: required
		Value type: <prop-encoded-array>
		Definition: Array which defines the register addresses of the L_VAL
		control register for each of the two clusters managed
		by the OSM controller.

		- qcom,apcs-itm-present
		Usage: required
		Value type: <prop-encoded-array>
		Definition: Array which defines the register addresses of the ITM
		control register for each of the two clusters managed
		by the OSM controller.

		- qcom,apcs-pll-user-ctl
		Usage: required
		Value type: <prop-encoded-array>
		Definition: Array which defines the register addresses of the PLL
		user control register for each of the two clusters managed
		by the OSM controller.

		- qcom,apcs-cfg-rcgr
		Usage: required
		Value type: <prop-encoded-array>
		Definition: Array which defines the register addresses of the RCGR
		configuration register for each of the two clusters managed
		by the OSM controller.

		- qcom,apcs-cmd-rcgr
		Usage: required
		Value type: <prop-encoded-array>
		Definition: Array which defines the register addresses of the RCGR
		command register for each of the two clusters managed
		by the OSM controller.

		- qcom,apm-threshold-voltage
		Usage: required
		Value type: <u32>
		Definition: Specifies the APM threshold voltage in microvolts. If the
		VDD_APCC supply voltage is above or at this level, then the
		APM is switched to use VDD_APCC. If VDD_APCC is below
		this level, then the APM is switched to use VDD_MX.

		- qcom,apm-mode-ctl
		Usage: required
		Value type: <prop-encoded-array>
		Definition: Array which defines the register addresses of the APM
		control register for each of the two clusters managed
		by the OSM controller.

		- qcom,apm-ctrl-status
		Usage: required
		Value type: <prop-encoded-array>
		Definition: Array which defines the register addresses of the APM
		controller status register for each of the two clusters
		managed by the OSM controller.

		- qcom,llm-sw-overr
		Usage: optional
		Value type: <prop-encoded-array>
		Definition: Array of tuples which defines the three non-zero LLM SW
		override values to write to the OSM controller for each
		of the two clusters. Each tuple must contain three elements.

		- qcom,acdtd-val
		Usage: required if pwrcl_acd or perfcl_acd registers are specified
		Value type: <prop-encoded-array>
		Definition: Array which defines the values to program to the ACD
		Tunable-Length Delay register for the power and performance
		clusters.

		- qcom,acdcr-val
		Usage: required if pwrcl_acd or perfcl_acd registers are specified
		Value type: <prop-encoded-array>
		Definition: Array which defines the values for the ACD control register
		for the power and performance clusters.

		- qcom,acdsscr-val
		Usage: required if pwrcl_acd or perfcl_acd registers are specified
		Value type: <prop-encoded-array>
		Definition: Array which defines the values for the ACD Soft Start Control
		register for the power and performance clusters.

		- qcom,acdextint0-val
		Usage: required if pwrcl_acd or perfcl_acd registers are specified
		Value type: <prop-encoded-array>
		Definition: Array which defines the initial values for the ACD
		external interface configuration register for the power
		and performance clusters.

		- qcom,acdextint1-val
		Usage: required if pwrcl_acd or perfcl_acd registers are specified
		Value type: <prop-encoded-array>
		Definition: Array which defines the final values for the ACD
		external interface configuration register for the power
		and performance clusters.

		- qcom,acdautoxfer-val
		Usage: required if pwrcl_acd or perfcl_acd registers are specified
		Value type: <prop-encoded-array>
		Definition: Array which defines the values for the ACD auto transfer
		control register for the power and performance clusters.

		- qcom,pwrcl-apcs-mem-acc-cfg
		Usage: required if qcom,osm-no-tz is specified
		Value type: <prop-encoded-array>
		Definition: Array which defines the addresses of the mem-acc
		configuration registers for the Power cluster.
		The array must contain exactly three elements.

		- qcom,perfcl-apcs-mem-acc-cfg
		Usage: required if qcom,osm-no-tz is specified
		Value type: <prop-encoded-array>
		Definition: Array which defines the addresses of the mem-acc
		configuration registers for the Performance cluster.
		The array must contain exactly three elements.

		- qcom,pwrcl-apcs-mem-acc-val
		Usage: required if qcom,osm-no-tz is specified
		Value type: <prop-encoded-array>
		Definition: List of integer tuples which define the mem-acc values
		for each performance mode of the Power cluster. Each tuple
		is of length 3 corresponding to the mem-acc values per
		performance mode with a total of 4 tuples corresponding
		to each supported performance mode.

		- qcom,pwrcl-apcs-mem-acc-threshold-voltage
		Usage: optional
		Value type: <u32>
		Definition: Specifies the highest MEM ACC threshold voltage in
		microvolts for the Power cluster. This voltage is
		used to determine which MEM ACC setting is used for the
		highest frequencies. If specified, the voltage must match
		the MEM ACC threshold voltage specified for the
		corresponding CPRh device.

		- qcom,perfcl-apcs-mem-acc-val
		Usage: required if qcom,osm-no-tz is specified
		Value type: <prop-encoded-array>
		Definition: List of integer tuples which define the mem-acc values
		for each performance mode of the Performance cluster.
		Each tuple is of length 3 corresponding to the mem-acc
		values per performance mode with a total of 4 tuples
		corresponding to each supported performance mode.

		- qcom,perfcl-apcs-mem-acc-threshold-voltage
		Usage: optional
		Value type: <u32>
		Definition: Specifies the highest MEM ACC threshold voltage in
		microvolts for the Performance cluster. This voltage is
		used to determine which MEM ACC setting is used for the
		highest frequencies. If specified, the voltage must match
		the MEM ACC threshold voltage specified for the
		corresponding CPRh device.

		- qcom,red-fsm-en
		Usage: optional
		Value type: <empty>
		Definition: Boolean flag which indicates if the reduction FSM
		should be enabled.

		- qcom,boost-fsm-en
		Usage: optional
		Value type: <empty>
		Definition: Boolean flag which indicates if the boost FSM should
		be enabled.

		- qcom,safe-fsm-en
		Usage: optional
		Value type: <empty>
		Definition: Boolean flag which indicates if the safe FSM should
		be enabled.

		- qcom,ps-fsm-en
		Usage: optional
		Value type: <empty>
		Definition: Boolean flag which indicates if the PS FSM should be
		enabled.

		- qcom,droop-fsm-en
		Usage: optional
		Value type: <empty>
		Definition: Boolean flag which indicates if the droop FSM should
		be enabled.
		- qcom,wfx-fsm-en
		Usage: optional
		Value type: <empty>
		Definition: Boolean flag which indicates if the WFX FSM should
		be enabled.

		- qcom,pc-fsm-en
		Usage: optional
		Value type: <empty>
		Definition: Boolean flag which indicates if the PC/RET FSM should
		be enabled.

		- clock-names
		Usage: required
		Value type: <string>
		Definition: Must be "aux_clk".

		- clocks
		Usage: required
		Value type: <phandle>
		Definition: Phandle to the aux clock device.

		Example:

		clock_cpu: qcom,clk-cpu-660@179c0000 {
		compatible = "qcom,clk-cpu-osm";
		reg = <0x179c0000 0x4000>, <0x17916000 0x1000>,
		<0x17816000 0x1000>, <0x179d1000 0x1000>,
		<0x00784130 0x8>, <0x00784130 0x8>;
		reg-names = "osm", "pwrcl_pll", "perfcl_pll",
		"apcs_common", "pwrcl_efuse",
		"perfcl_efuse";

		vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
		vdd-perfcl-supply = <&apc1_perfcl_vreg>;

		interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
		<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "pwrcl-irq", "perfcl-irq";

		qcom,pwrcl-speedbin0-v0 =
		< 300000000 0x0004000f 0x01200020 0x1 1 >,
		< 633600000 0x05040021 0x03200020 0x1 2 >,
		< 902400000 0x0404002f 0x04260026 0x1 3 >,
		< 1113600000 0x0404003a 0x052e002e 0x2 4 >,
		< 1401600000 0x04040049 0x073a003a 0x2 5 >,
		< 1536000000 0x04040050 0x08400040 0x2 6 >,
		< 1747200000 0x0404005b 0x09480048 0x2 7 >,
		< 1843200000 0x04040060 0x094c004c 0x3 8 >;

		qcom,pwrcl-speedbin1-v0 =
		< 300000000 0x0004000f 0x01200020 0x1 1 >,
		< 633600000 0x05040021 0x03200020 0x1 2 >,
		< 902400000 0x0404002f 0x04260026 0x1 3 >,
		< 1113600000 0x0404003a 0x052e002e 0x2 4 >,
		< 1401600000 0x04040049 0x073a003a 0x2 5 >,
		< 1536000000 0x04040050 0x08400040 0x2 6 >,
		< 1747200000 0x0404005b 0x09480048 0x2 7 >,
		< 1843200000 0x04040060 0x094c004c 0x3 8 >;

		qcom,pwrcl-speedbin3-v0 =
		< 300000000 0x0004000f 0x01200020 0x1 1 >,
		< 633600000 0x05040021 0x03200020 0x1 2 >,
		< 902400000 0x0404002f 0x04260026 0x1 3 >,
		< 1113600000 0x0404003a 0x052e002e 0x2 4 >,
		< 1401600000 0x04040049 0x073a003a 0x2 5 >,
		< 1536000000 0x04040050 0x08400040 0x2 6 >,
		< 1612800000 0x04040054 0x09430043 0x2 7 >;

		qcom,pwrcl-speedbin4-v0 =
		< 300000000 0x0004000f 0x01200020 0x1 1 >,
		< 633600000 0x05040021 0x03200020 0x1 2 >,
		< 902400000 0x0404002f 0x04260026 0x1 3 >,
		< 1113600000 0x0404003a 0x052e002e 0x2 4 >,
		< 1401600000 0x04040049 0x073a003a 0x2 5 >,
		< 1536000000 0x04040050 0x08400040 0x2 6 >,
		< 1747200000 0x0404005b 0x09480048 0x2 7 >,
		< 1843200000 0x04040060 0x094c004c 0x3 8 >;

		qcom,perfcl-speedbin0-v0 =
		< 300000000 0x0004000f 0x01200020 0x1 1 >,
		< 1113600000 0x0404003a 0x052e002e 0x1 2 >,
		< 1401600000 0x04040049 0x073a003a 0x2 3 >,
		< 1747200000 0x0404005b 0x09480048 0x2 4 >,
		< 1958400000 0x04040066 0x0a510051 0x2 5 >,
		< 2150400000 0x04040070 0x0b590059 0x2 6 >,
		< 2457600000 0x04040080 0x0c660066 0x3 7 >;

		qcom,perfcl-speedbin1-v0 =
		< 300000000 0x0004000f 0x01200020 0x1 1 >,
		< 1113600000 0x0404003a 0x052e002e 0x1 2 >,
		< 1401600000 0x04040049 0x073a003a 0x2 3 >,
		< 1747200000 0x0404005b 0x09480048 0x2 4 >,
		< 1958400000 0x04040066 0x0a510051 0x2 5 >,
		< 2150400000 0x04040070 0x0b590059 0x2 6 >,
		< 2208000000 0x04040073 0x0b5c005c 0x3 7 >;

		qcom,perfcl-speedbin3-v0 =
		< 300000000 0x0004000f 0x01200020 0x1 1 >,
		< 1113600000 0x0404003a 0x052e002e 0x1 2 >,
		< 1401600000 0x04040049 0x073a003a 0x2 3 >,
		< 1747200000 0x0404005b 0x09480048 0x2 4 >,
		< 1804800000 0x0404005e 0x094b004b 0x2 5 >;

		qcom,perfcl-speedbin4-v0 =
		< 300000000 0x0004000f 0x01200020 0x1 1 >,
		< 1113600000 0x0404003a 0x052e002e 0x1 2 >,
		< 1401600000 0x04040049 0x073a003a 0x2 3 >,
		< 1747200000 0x0404005b 0x09480048 0x2 4 >,
		< 1958400000 0x04040066 0x0a510051 0x2 5 >;

		qcom,up-timer = <1000 1000>;
		qcom,down-timer = <1000 1000>;
		qcom,set-ret-inactive;
		qcom,enable-llm-freq-vote;
		qcom,llm-freq-up-timer = <327675 327675>;
		qcom,llm-freq-down-timer = <327675 327675>;
		qcom,enable-llm-volt-vote;
		qcom,llm-volt-up-timer = <327675 327675>;
		qcom,llm-volt-down-timer = <327675 327675>;
		qcom,cc-reads = <10>;
		qcom,cc-delay = <5>;
		qcom,cc-factor = <100>;
		qcom,osm-clk-rate = <200000000>;
		qcom,xo-clk-rate = <19200000>;

		qcom,l-val-base = <0x17916004 0x17816004>;
		qcom,apcs-itm-present = <0x179d143c 0x179d143c>;
		qcom,apcs-pll-user-ctl = <0x1791600c 0x1781600c>;
		qcom,apcs-cfg-rcgr = <0x17911054 0x17811054>;
		qcom,apcs-cmd-rcgr = <0x17911050 0x17811050>;
		qcom,apm-mode-ctl = <0x179d0004 0x179d0010>;
		qcom,apm-ctrl-status = <0x179d000c 0x179d0018>;

		qcom,apm-threshold-voltage = <872000>;
		qcom,boost-fsm-en;
		qcom,safe-fsm-en;
		qcom,ps-fsm-en;
		qcom,droop-fsm-en;
		qcom,wfx-fsm-en;
		qcom,pc-fsm-en;

		clock-names = "aux_clk", "xo_a";
		clocks = <&clock_gcc HMSS_GPLL0_CLK_SRC>,
		<&clock_rpmcc RPM_XO_A_CLK_SRC>;

		#clock-cells = <1>;
		};

bindings/arm/msm/spm-v2.txt

0 → 100644

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Original line number	Diff line number	Diff line
		* MSM Subsystem Power Manager (spm-v2)

		S4 generation of MSMs have SPM hardware blocks to control the Application
		Processor Sub-System power. These SPM blocks run individual state machine
		to determine what the core (L2 or Krait/Scorpion) would do when the WFI
		instruction is executed by the core. The SAW hardware block handles SPM and
		AVS functionality for the cores.

		The devicetree representation of the SPM block should be:

		Required properties

		- compatible: "qcom,spm-v2"
		- reg: The physical address and the size of the SPM's memory mapped registers
		- qcom,cpu: phandle for the CPU that the SPM block is attached to. This field
		is required on only for SPMs that control the CPU. This field is not required
		for SPMs that control L2/CCI/L3
		- qcom,saw2-ver-reg: The location of the version register
		- qcom,name: The name with which a SPM device is identified by the power
		management code.

		----------------------------------------------------
		Non-PSCI targets should follow the rules shown below
		----------------------------------------------------
		Required properties for only Non-PSCI targets:

		- qcom,saw2-cfg: SAW2 configuration register
		- qcom,saw2-spm-ctl: The SPM control register
		- qcom,saw2-spm-dly: Provides the values for the SPM delay command in the SPM
		sequence

		Optional properties for only Non-PSCI targets
		- reg-names: Register names for the physical address required if spm device
		has more than one physical addressed to be mapped. Allowed register
		names are: "saw-base", "q2s", "hw-flush", "slpreq"
		- qcom,saw2-avs-ctl: The AVS control register
		- qcom,saw2-avs-hysterisis: The AVS hysterisis register to delay the AVS
		controller requests
		- qcom,vctl-timeout-us: The timeout value in us to wait for voltage to change
		after sending the voltage command to the PMIC
		- qcom,saw2-avs-limit: The AVS limit register
		- qcom,saw2-avs-dly: The AVS delay register is used to specify the delay values
		between AVS controller requests
		- qcom,saw2-pmic-data0..7: Specify the pmic data value and the associated FTS
		index to send the PMIC data to
		- qcom,vctl-port: The PVC (PMIC Virtual Channel) port used for changing
		voltage
		- qcom,vctl-port-ub: The PVC (PMIC Virtual Channel) port used for changing
		voltage
		- qcom,phase-port: The PVC port used for changing the number of phases
		- qcom,pfm-port: The PVC port used for enabling PWM/PFM modes
		- qcom,cpu-vctl-mask: Mask of cpus, whose voltage the spm device can control.
		Depricated: Replaced with cpu-vctl-list when cpu phandles are available.
		- qcom,cpu-vctl-list: List of cpu node phandles, whose voltage the spm device
		can control.
		- qcom,use-qchannel-for-pc: Boolean property to specify if qchannel should be
		ignored when entering power collapse. If this property is set qchannel
		will not be ignored in power collapse.
		- qcom,supports-rpm-hs: Indicates that this SPM instance allow handshake with
		RPM processor when executing the sleep command in the SPM sequence. Supported
		only on SAW2 v3.0 and above.
		- qcom,use-spm-clock-gating: This boolean property is used to indicate that
		the SPM needs to be used for clock gating. Using the SPM for clock
		gating would result in auto clock gating being disabled. Use this on
		targets that do not support or do not use auto clock gating.
		- qcom,use-qchannel-for-wfi: This boolean property is used to indicate
		that the SPM gets triggerd by the qchannel and not by means of
		wfi. So a wfe could trigger a spm for clock gating as well.
		- modes: Lists all the available low power modes for the device

		Second level properties for modes

		Required properties (if modes node is available)
		- qcom,label: Specifies the mode name such as:
		qcom,saw2-spm-cmd-wfi: WFI mode
		qcom,saw2-spm-cmd-ret: Retention mode
		qcom,saw2-spm-cmd-spc: Standalone PC mode
		qcom,saw2-spm-cmd-pc: Power Collapse mode
		qcom,saw2-spm-cmd-gdhs: GDHS mode
		- qcom,sequence: Specifies sequence for the low power mode
		Optional properties
		- qcom,pc_mode: Specifies pc_mode bit should be set in the SPM control register
		- qcom,ret_mode: Specifies ret_mode bit should be set in the SPM control register
		- qcom,spm_en: Specifies spm_en bit should be set in the SPM control register
		- qcom,isar: Specifies isar bit should be set in the SPM control register
		Specify this property only if SPM should retain its start address at
		the end of the program.
		- qcom,slp_cmd_mode: Specifies slp_cmd_mode bit should be set in SPM control register.
		Adding this property results in SPM handshaking with RPM. Please remove
		the RPM handshake command from the sleep sequence, replace that with
		Sleep without RPM handshake command.
		- qcom,event_sync: Specifies event_sync byte should be set in SPM control
		register.

		----------------------------------------------------
		PSCI targets should follow the rules shown below
		----------------------------------------------------
		Optional properties for only PSCI targets:

		- qcom,saw2-avs-ctl: The AVS control register
		- qcom,saw2-avs-hysterisis: The AVS hysterisis register to delay the AVS
		controller requests
		- qcom,vctl-timeout-us: The timeout value in us to wait for voltage to change
		after sending the voltage command to the PMIC
		- qcom,saw2-avs-limit: The AVS limit register
		- qcom,saw2-avs-dly: The AVS delay register is used to specify the delay values
		between AVS controller requests
		- qcom,vctl-port: The PVC (PMIC Virtual Channel) port used for changing
		voltage
		- qcom,vctl-port-ub: The PVC (PMIC Virtual Channel) port used for changing
		voltage
		- qcom,phase-port: The PVC port used for changing the number of phases
		- qcom,pfm-port: The PVC port used for enabling PWM/PFM modes
		- qcom,cpu-vctl-list: List of cpu node phandles, whose voltage the spm device
		can control.


		Example 1:
		qcom,spm@f9089000 {
		compatible = "qcom,spm-v2";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0xf9089000 0x1000>;
		qcom,cpu = <&CPU0>;
		qcom,saw2-ver-reg = <0xfd0>;
		qcom,saw2-cfg = <0x1b>;
		qcom,saw2-avs-ctl = <0>;
		qcom,saw2-avs-hysteresis = <0>;
		qcom,saw2-avs-limit = <0>;
		qcom,saw2-avs-dly= <0>;
		qcom,saw2-spm-dly= <0x20000400>;
		qcom,saw2-spm-ctl = <0x1>;
		qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>;
		qcom,mode0 {
		qcom,label = "qcom,saw2-spm-cmd-wfi";
		qcom,sequence = [03 0b 0f];
		qcom,spm_en;
		};

		qcom,mode1 {
		qcom,label = "qcom,saw2-spm-cmd-spc";
		qcom,sequence = [00 20 50 80 60 70 10 92
		a0 b0 03 68 70 3b 92 a0 b0
		82 2b 50 10 30 02 22 30 0f];
		qcom,spm_en;
		qcom,pc_mode;
		};

		qcom,mode2 {
		qcom,label = "qcom,saw2-spm-cmd-pc";
		qcom,sequence = [00 20 10 92 a0 b0 07 3b 92
		a0 b0 82 10 30 02 22 30 0f];
		qcom,spm_en;
		qcom,pc_mode;
		};
		};

		Example 2:
		qcom,spm@9A10000 {
		compatible = "qcom,spm-v2";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x9A10000 0x1000>;
		qcom,name = "system-cbf"; /* CBF SAW */
		qcom,saw2-ver-reg = <0xFD0>;
		qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>;
		qcom,vctl-timeout-us = <50>;
		qcom,vctl-port = <0x0>;
		qcom,phase-port = <0x1>;
		qcom,saw2-avs-ctl = <0x1100>;
		qcom,pfm-port = <0x2>;
		};

bindings/clock/qcom,debugcc.txt

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bindings/clock/qcom,gcc.txt

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Original line number	Diff line number	Diff line
		@@ -24,7 +24,7 @@ Required properties :
		"qcom,gcc-lito"
		"qcom,bengal-gcc"
		"qcom,lagoon-gcc"
		"qcom,scuba-gcc".
		"qcom,gcc-sdm660"

		- reg : shall contain base register location and length
		- #clock-cells : shall contain 1