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Commit c3424e1c authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'socfpga_dts_for_v4.10_part_1' of... 

Merge tag 'socfpga_dts_for_v4.10_part_1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt

SoCFPGA DTS update for v4.10, part 1
- Add a Macnica sodia board
- Add support for the Arria10 System resource device
- Add support for the Arria10 LEDs
- Add QSPI to the socrates board
- Update L2 cache settings, enabling arm,shared-override

* tag 'socfpga_dts_for_v4.10_part_1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux

:
  ARM: dts: socfpga: socrates: enable qspi
  ARM: dts: socfpga: add qspi node
  ARM: dts: socfpga: Add LED framework to A10-SR GPIO
  ARM: dts: socfpga: Enable GPIO parent for Arria10 SR chip
  ARM: dts: socfpga: Add Devkit A10-SR fields for Arria10
  ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chip
  ARM: dts: socfpga: enable arm,shared-override in the pl310
  ARM: dts: socfpga: Add Macnica sodia board
  ARM: dts: socfpga: Add new MCVEVK manufacturer compat

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents fbea3a0f c96f5919

arch/arm/boot/dts/Makefile

+1 −0
Original line number Original line Diff line number Diff line
@@ -696,6 +696,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ 
	socfpga_cyclone5_de0_sockit.dtb \

	socfpga_cyclone5_de0_sockit.dtb \

	socfpga_cyclone5_sockit.dtb \

	socfpga_cyclone5_sockit.dtb \

	socfpga_cyclone5_socrates.dtb \

	socfpga_cyclone5_socrates.dtb \

	socfpga_cyclone5_sodia.dtb \

	socfpga_cyclone5_vining_fpga.dtb \

	socfpga_cyclone5_vining_fpga.dtb \

	socfpga_vt.dtb

	socfpga_vt.dtb

dtb-$(CONFIG_ARCH_SPEAR13XX) += \

dtb-$(CONFIG_ARCH_SPEAR13XX) += \

arch/arm/boot/dts/socfpga.dtsi

+15 −0
Original line number Original line Diff line number Diff line
@@ -686,6 +686,7 @@ 
			arm,data-latency = <2 1 1>;

			arm,data-latency = <2 1 1>;

			prefetch-data = <1>;

			prefetch-data = <1>;

			prefetch-instr = <1>;

			prefetch-instr = <1>;

			arm,shared-override;

		};

		};





		mmc: dwmmc0@ff704000 {

		mmc: dwmmc0@ff704000 {
@@ -705,6 +706,20 @@ 
			reg = <0xffff0000 0x10000>;

			reg = <0xffff0000 0x10000>;

		};

		};





		qspi: spi@ff705000 {

			compatible = "cdns,qspi-nor";

                        #address-cells = <1>;

			#size-cells = <0>;

			reg = <0xff705000 0x1000>,

			      <0xffa00000 0x1000>;

			interrupts = <0 151 4>;

			cdns,fifo-depth = <128>;

			cdns,fifo-width = <4>;

			cdns,trigger-address = <0x00000000>;

			clocks = <&qspi_clk>;

			status = "disabled";

		};



		rst: rstmgr@ffd05000 {

		rst: rstmgr@ffd05000 {

			#reset-cells = <1>;

			#reset-cells = <1>;

			compatible = "altr,rst-mgr";

			compatible = "altr,rst-mgr";

arch/arm/boot/dts/socfpga_arria10.dtsi

+18 −0
Original line number Original line Diff line number Diff line
@@ -562,6 +562,21 @@ 
			status = "disabled";

			status = "disabled";

		};

		};





		spi1: spi@ffda5000 {

			compatible = "snps,dw-apb-ssi";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0xffda5000 0x100>;

			interrupts = <0 102 4>;

			num-chipselect = <4>;

			bus-num = <0>;

			/*32bit_access;*/

			tx-dma-channel = <&pdma 16>;

			rx-dma-channel = <&pdma 17>;

			clocks = <&spi_m_clk>;

			status = "disabled";

		};



		sdr: sdr@ffc25000 {

		sdr: sdr@ffc25000 {

			compatible = "syscon";

			compatible = "syscon";

			reg = <0xffcfb100 0x80>;

			reg = <0xffcfb100 0x80>;
@@ -573,6 +588,9 @@ 
			interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;

			cache-unified;

			cache-unified;

			cache-level = <2>;

			cache-level = <2>;

			prefetch-data = <1>;

			prefetch-instr = <1>;

			arm,shared-override;

		};

		};





		mmc: dwmmc0@ff808000 {

		mmc: dwmmc0@ff808000 {

arch/arm/boot/dts/socfpga_arria10_socdk.dtsi

+49 −0
Original line number Original line Diff line number Diff line
@@ -36,6 +36,30 @@ 
		reg = <0x0 0x40000000>; /* 1GB */

		reg = <0x0 0x40000000>; /* 1GB */

	};

	};





	a10leds {

		compatible = "gpio-leds";



		a10sr_led0 {

			label = "a10sr-led0";

			gpios = <&a10sr_gpio 0 1>;

		};



		a10sr_led1 {

			label = "a10sr-led1";

			gpios = <&a10sr_gpio 1 1>;

		};



		a10sr_led2 {

			label = "a10sr-led2";

			gpios = <&a10sr_gpio 2 1>;

		};



		a10sr_led3 {

			label = "a10sr-led3";

			gpios = <&a10sr_gpio 3 1>;

		};

	};



	soc {

	soc {

		clkmgr@ffd04000 {

		clkmgr@ffd04000 {

			clocks {

			clocks {
@@ -75,6 +99,31 @@ 
	status = "okay";

	status = "okay";

};

};





&gpio1 {

	status = "okay";

};



&spi1 {

	status = "okay";



	resource-manager@0 {

		compatible = "altr,a10sr";

		reg = <0>;

		spi-max-frequency = <100000>;

		/* low-level active IRQ at GPIO1_5 */

		interrupt-parent = <&portb>;

		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;

		interrupt-controller;

		#interrupt-cells = <2>;



		a10sr_gpio: gpio-controller {

			compatible = "altr,a10sr-gpio";

			gpio-controller;

			#gpio-cells = <2>;

		};

	};

};



&i2c1 {

&i2c1 {

	speed-mode = <0>;

	speed-mode = <0>;

	status = "okay";

	status = "okay";

arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi

+1 −1
Original line number Original line Diff line number Diff line
@@ -18,7 +18,7 @@ 
#include "socfpga_cyclone5.dtsi"

#include "socfpga_cyclone5.dtsi"





/ {

/ {

	model = "DENX MCV";

	model = "Aries/DENX MCV";

	compatible = "altr,socfpga-cyclone5", "altr,socfpga";

	compatible = "altr,socfpga-cyclone5", "altr,socfpga";





	memory {

	memory {