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Commit c2f95279 authored by Michael Hennerich's avatar Michael Hennerich Committed by Bryan Wu
Browse files

[Blackfin] arch: Equalize include files: Add VR_CTL masks 



Signed-off-by: default avatarMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent 67dea022

include/asm-blackfin/mach-bf533/defBF532.h

+2 −0
Original line number Diff line number Diff line
@@ -468,6 +468,8 @@ 
#define	VLEV_110		0x00B0	/* 		VLEV = 1.10 V (-5% - +10% Accuracy)	*/

#define	VLEV_115		0x00C0	/* 		VLEV = 1.15 V (-5% - +10% Accuracy)	*/

#define	VLEV_120		0x00D0	/* 		VLEV = 1.20 V (-5% - +10% Accuracy)	*/

#define	VLEV_125		0x00E0	/*              VLEV = 1.25 V (-5% - +10% Accuracy)     */

#define	VLEV_130		0x00F0	/*              VLEV = 1.30 V (-5% - +10% Accuracy)     */



#define	WAKE			0x0100	/* Enable RTC/Reset Wakeup From Hibernate	*/

#define	SCKELOW			0x8000	/* Do Not Drive SCKE High During Reset After Hibernate */

include/asm-blackfin/mach-bf548/defBF54x_base.h

+20 −0
Original line number Diff line number Diff line
@@ -2329,6 +2329,26 @@ 
#define                    KPADWE  0x1000     /* Keypad Wake-Up Enable */

#define                     ROTWE  0x2000     /* Rotary Wake-Up Enable */



#define	FREQ_333		0x0001	/* Switching Frequency Is 333 kHz */

#define	FREQ_667		0x0002	/* Switching Frequency Is 667 kHz */

#define	FREQ_1000		0x0003	/* Switching Frequency Is 1 MHz */



#define	GAIN_5			0x0000	/* GAIN = 5*/

#define	GAIN_10			0x0004	/* GAIN = 1*/

#define	GAIN_20			0x0008	/* GAIN = 2*/

#define	GAIN_50			0x000C	/* GAIN = 5*/



#define	VLEV_085 		0x0060	/* VLEV = 0.85 V (-5% - +10% Accuracy) */

#define	VLEV_090		0x0070	/* VLEV = 0.90 V (-5% - +10% Accuracy) */

#define	VLEV_095		0x0080	/* VLEV = 0.95 V (-5% - +10% Accuracy) */

#define	VLEV_100		0x0090	/* VLEV = 1.00 V (-5% - +10% Accuracy) */

#define	VLEV_105		0x00A0	/* VLEV = 1.05 V (-5% - +10% Accuracy) */

#define	VLEV_110		0x00B0	/* VLEV = 1.10 V (-5% - +10% Accuracy) */

#define	VLEV_115		0x00C0	/* VLEV = 1.15 V (-5% - +10% Accuracy) */

#define	VLEV_120		0x00D0	/* VLEV = 1.20 V (-5% - +10% Accuracy) */

#define	VLEV_125		0x00E0	/* VLEV = 1.25 V (-5% - +10% Accuracy) */

#define	VLEV_130		0x00F0	/* VLEV = 1.30 V (-5% - +10% Accuracy) */



/* Bit masks for NFC_CTL */



#define                    WR_DLY  0xf        /* Write Strobe Delay */

include/asm-blackfin/mach-bf561/defBF561.h

+28 −0
Original line number Diff line number Diff line
@@ -868,6 +868,34 @@ 
#define CHIPID_FAMILY          0x0FFFF000

#define CHIPID_MANUFACTURE     0x00000FFE



/* VR_CTL Masks																	*/

#define	FREQ			0x0003	/* Switching Oscillator Frequency For Regulator	*/

#define	HIBERNATE		0x0000	/* Powerdown/Bypass On-Board Regulation	*/

#define	FREQ_333		0x0001	/* Switching Frequency Is 333 kHz */

#define	FREQ_667		0x0002	/* Switching Frequency Is 667 kHz */

#define	FREQ_1000		0x0003	/* Switching Frequency Is 1 MHz */



#define	GAIN			0x000C	/* Voltage Level Gain	*/

#define	GAIN_5			0x0000	/* GAIN = 5*/

#define	GAIN_10			0x0004	/* GAIN = 1*/

#define	GAIN_20			0x0008	/* GAIN = 2*/

#define	GAIN_50			0x000C	/* GAIN = 5*/



#define	VLEV			0x00F0	/* Internal Voltage Level */

#define	VLEV_085 		0x0060	/* VLEV = 0.85 V (-5% - +10% Accuracy) */

#define	VLEV_090		0x0070	/* VLEV = 0.90 V (-5% - +10% Accuracy) */

#define	VLEV_095		0x0080	/* VLEV = 0.95 V (-5% - +10% Accuracy) */

#define	VLEV_100		0x0090	/* VLEV = 1.00 V (-5% - +10% Accuracy) */

#define	VLEV_105		0x00A0	/* VLEV = 1.05 V (-5% - +10% Accuracy) */

#define	VLEV_110		0x00B0	/* VLEV = 1.10 V (-5% - +10% Accuracy) */

#define	VLEV_115		0x00C0	/* VLEV = 1.15 V (-5% - +10% Accuracy) */

#define	VLEV_120		0x00D0	/* VLEV = 1.20 V (-5% - +10% Accuracy) */

#define	VLEV_125		0x00E0	/* VLEV = 1.25 V (-5% - +10% Accuracy) */

#define	VLEV_130		0x00F0	/* VLEV = 1.30 V (-5% - +10% Accuracy) */



#define	WAKE			0x0100	/* Enable RTC/Reset Wakeup From Hibernate */

#define	SCKELOW			0x8000	/* Do Not Drive SCKE High During Reset After Hibernate */



/* PLL_DIV Masks */

#define SCLK_DIV(x)  (x)	/* SCLK = VCO / x */