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Commit c2e4c049 authored by Shefali Jain's avatar Shefali Jain Committed by Taniya Das
Browse files

ARM: dts: msm: Update DISPCC clock node for LITO 



Update the display clock node to use the display
clock driver. Also, update the display GDSCs to
use the regulator driver.

Change-Id: Ic3f8cbaeca508c5c1f6ad667a3a3de907c37e7d0
Signed-off-by: default avatarShefali Jain <shefjain@codeaurora.org>
parent 903739c8

arch/arm64/boot/dts/qcom/lito-gdsc.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -91,7 +91,7 @@ 


	/* DISP_CC GDSC */

	mdss_core_gdsc: qcom,gdsc@af03000 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xaf03000 0x4>;

		regulator-name = "mdss_core_gdsc";

		qcom,support-hw-trigger;

arch/arm64/boot/dts/qcom/lito.dtsi

+13 −7
Original line number Diff line number Diff line
@@ -911,6 +911,17 @@ 
		#reset-cells = <1>;

	};



	dispcc: qcom,dispcc {

		compatible = "qcom,lito-dispcc";

		reg = <0xaf00000 0x20000>;

		reg-names = "cc_base";

		clock-names = "cfg_ahb_clk";

		clocks = <&gcc GCC_DISP_AHB_CLK>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	ufsphy_mem: ufsphy_mem@1d87000 {

		reg = <0x1d87000 0xe00>; /* PHY regs */

		reg-names = "phy_mem";
@@ -1044,13 +1055,6 @@ 
		#reset-cells = <1>;

	};



	dispcc: qcom,dispcc {

		compatible = "qcom,dummycc";

		clock-output-names = "dispcc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	gpucc: qcom,gpucc {

		compatible = "qcom,dummycc";

		clock-output-names = "gpucc_clocks";
@@ -1485,6 +1489,8 @@ 
};



&mdss_core_gdsc {

	clock-names = "ahb_clk";

	clocks = <&gcc GCC_DISP_AHB_CLK>;

	status = "ok";

};