Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux

  weblink : http://www.st.com/spear

  The ST Microelectronics SPEAr range of ARM9/CortexA9 System-on-Chip CPUs are

  supported by the 'spear' platform of ARM Linux. Currently SPEAr300,

  SPEAr310, SPEAr320 and SPEAr600 SOCs are supported. Support for the SPEAr13XX

  series is in progress.

  supported by the 'spear' platform of ARM Linux. Currently SPEAr1310,

  SPEAr1340, SPEAr300, SPEAr310, SPEAr320 and SPEAr600 SOCs are supported.

  Hierarchy in SPEAr is as follows:

		- SPEAr600 (SOC)

			- SPEAr600 Evaluation Board

	- SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)

		- SPEAr1300 (SOC)

		- SPEAr1310 (SOC)

			- SPEAr1310 Evaluation Board

		- SPEAr1340 (SOC)

			- SPEAr1340 Evaluation Board

  Configuration

  -------------

  A generic configuration is provided for each machine, and can be used as the

  default by

	make spear600_defconfig

	make spear300_defconfig

	make spear310_defconfig

	make spear320_defconfig

	make spear13xx_defconfig

	make spear3xx_defconfig

	make spear6xx_defconfig

  Layout

  ------

  The common files for multiple machine families (SPEAr3XX, SPEAr6XX and

  SPEAr13XX) are located in the platform code contained in arch/arm/plat-spear

  The common files for multiple machine families (SPEAr3xx, SPEAr6xx and

  SPEAr13xx) are located in the platform code contained in arch/arm/plat-spear

  with headers in plat/.

  Each machine series have a directory with name arch/arm/mach-spear followed by

  series name. Like mach-spear3xx, mach-spear6xx and mach-spear13xx.

  Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for

  spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine

  specific files, like spear300.c, spear310.c, spear320.c and spear600.c.

  mach-spear* doesn't contains board specific files as they fully support

  Flattened Device Tree.

  Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c, for

  spear6xx is mach-spear6xx/spear6xx.c and for spear13xx family is

  mach-spear13xx/spear13xx.c. mach-spear* also contain soc/machine specific

  files, like spear1310.c, spear1340.c spear300.c, spear310.c, spear320.c and

  spear600.c.  mach-spear* doesn't contains board specific files as they fully

  support Flattened Device Tree.

  Document Author

Linux 2.4 on the CRIS architecture

==================================

$Id: README,v 1.7 2001/04/19 12:38:32 bjornw Exp $

Linux on the CRIS architecture

==============================

This is a port of Linux 2.4 to Axis Communications ETRAX 100LX embedded 

network CPU. For more information about CRIS and ETRAX please see further

below.

This is a port of Linux to Axis Communications ETRAX 100LX,

ETRAX FS and ARTPEC-3 embedded network CPUs.

For more information about CRIS and ETRAX please see further below.

In order to compile this you need a version of gcc with support for the

ETRAX chip family. Please see this link for more information on how to

download the compiler and other tools useful when building and booting

software for the ETRAX platform:

http://developer.axis.com/doc/software/devboard_lx/install-howto.html

<more specific information should come in this document later>

http://developer.axis.com/wiki/doku.php?id=axis:install-howto-2_20

What is CRIS ?

--------------

CRIS is an acronym for 'Code Reduced Instruction Set'. It is the CPU

architecture in Axis Communication AB's range of embedded network CPU's,

called ETRAX. The latest CPU is called ETRAX 100LX, where LX stands for

'Linux' because the chip was designed to be a good host for the Linux

operating system.

called ETRAX.

The ETRAX 100LX chip

--------------------

For reference, please see the press-release:

For reference, please see the following link:

http://www.axis.com/news/us/001101_etrax.htm

http://www.axis.com/products/dev_etrax_100lx/index.htm

The ETRAX 100LX is a 100 MIPS processor with 8kB cache, MMU, and a very broad

range of built-in interfaces, all with modern scatter/gather DMA.

	(not all interfaces are available at the same time due to chip pin

         multiplexing)

The previous version of the ETRAX, the ETRAX 100, sits in almost all of

Axis shipping thin-servers like the Axis 2100 web camera or the ETRAX 100

developer-board. It lacks an MMU so the Linux we run on that is a version

of uClinux (Linux 2.0 without MM-support) ported to the CRIS architecture.

The new Linux 2.4 port has full MM and needs a CPU with an MMU, so it will

not run on the ETRAX 100.

ETRAX 100LX is CRISv10 architecture.

The ETRAX FS and ARTPEC-3 chips

-------------------------------

The ETRAX FS is a 200MHz 32-bit RISC processor with on-chip 16kB

I-cache and 16kB D-cache and with a wide range of device interfaces

including multiple high speed serial ports and an integrated USB 1.1 PHY.

A version of the Axis developer-board with ETRAX 100LX (running Linux

2.4) is now available. For more information please see developer.axis.com.

The ARTPEC-3 is a variant of the ETRAX FS with additional IO-units

used by the Axis Communications network cameras.

See below link for more information:

http://www.axis.com/products/dev_etrax_fs/index.htm

ETRAX FS and ARTPEC-3 are both CRISv32 architectures.

Bootlog

-------

-rwxr-xr-x  1 342      100         16252  Jan 01 00:00 telnetd

(All programs are statically linked to the libc at this point - we have not ported the

 shared libraries yet)

Freescale i.MX Platforms Device Tree Bindings

-----------------------------------------------

i.MX23 Evaluation Kit

Required root node properties:

    - compatible = "fsl,imx23-evk", "fsl,imx23";

i.MX28 Evaluation Kit

Required root node properties:

    - compatible = "fsl,imx28-evk", "fsl,imx28";

i.MX51 Babbage Board

Required root node properties:

    - compatible = "fsl,imx51-babbage", "fsl,imx51";

Required root node properties:

    - compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";

i.MX6 Quad SABRE Smart Device Board

Required root node properties:

    - compatible = "fsl,imx6q-sabresd", "fsl,imx6q";

Generic i.MX boards

-------------------

* Samsung Exynos Interrupt Combiner Controller

Samsung's Exynos4 architecture includes a interrupt combiner controller which

can combine interrupt sources as a group and provide a single interrupt request

for the group. The interrupt request from each group are connected to a parent

interrupt controller, such as GIC in case of Exynos4210.

The interrupt combiner controller consists of multiple combiners. Upto eight

interrupt sources can be connected to a combiner. The combiner outputs one

combined interrupt for its eight interrupt sources. The combined interrupt

is usually connected to a parent interrupt controller.

A single node in the device tree is used to describe the interrupt combiner

controller module (which includes multiple combiners). A combiner in the

interrupt controller module shares config/control registers with other

combiners. For example, a 32-bit interrupt enable/disable config register

can accommodate upto 4 interrupt combiners (with each combiner supporting

upto 8 interrupt sources).

Required properties:

- compatible: should be "samsung,exynos4210-combiner".

- interrupt-controller: Identifies the node as an interrupt controller.

- #interrupt-cells: should be <2>. The meaning of the cells are

	* First Cell: Combiner Group Number.

	* Second Cell: Interrupt number within the group.

- reg: Base address and size of interrupt combiner registers.

- interrupts: The list of interrupts generated by the combiners which are then

    connected to a parent interrupt controller. The format of the interrupt

    specifier depends in the interrupt parent controller.

Optional properties:

- samsung,combiner-nr: The number of interrupt combiners supported. If this

  property is not specified, the default number of combiners is assumed

  to be 16.

- interrupt-parent: pHandle of the parent interrupt controller, if not

  inherited from the parent node.

Example:

	The following is a an example from the Exynos4210 SoC dtsi file.

	combiner:interrupt-controller@10440000 {

		compatible = "samsung,exynos4210-combiner";

		interrupt-controller;

		#interrupt-cells = <2>;

		reg = <0x10440000 0x1000>;

		interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,

			     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,

			     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,

			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;

	};

* SPEAr ARM Timer

** Timer node required properties:

- compatible : Should be:

	"st,spear-timer"

- reg: Address range of the timer registers

- interrupt-parent: Should be the phandle for the interrupt controller

  that services interrupts for this device

- interrupt: Should contain the timer interrupt number

Example:

	timer@f0000000 {

		compatible = "st,spear-timer";

		reg = <0xf0000000 0x400>;

		interrupts = <2>;

	};