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Commit c2c09ed5 authored by Mikita Lipski's avatar Mikita Lipski Committed by Alex Deucher
Browse files

drm/amd/display: add pp to dc powerlevel enum translator 



[why]
Add a switch statement to translate pp's powerlevel enum
to dc powerlevel statement enum
[how]
Add a translator function

Signed-off-by: default avatarMikita Lipski <mikita.lipski@amd.com>
Reviewed-by: default avatarSun peng Li <Sunpeng.Li@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8fc0a0d4

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

+28 −1
Original line number Diff line number Diff line
@@ -192,6 +192,33 @@ static enum amd_pp_clock_type dc_to_pp_clock_type( 
	return amd_pp_clk_type;

}



static enum dm_pp_clocks_state pp_to_dc_powerlevel_state(

			enum PP_DAL_POWERLEVEL max_clocks_state)

{

	switch (max_clocks_state) {

	case PP_DAL_POWERLEVEL_0:

		return DM_PP_CLOCKS_DPM_STATE_LEVEL_0;

	case PP_DAL_POWERLEVEL_1:

		return DM_PP_CLOCKS_DPM_STATE_LEVEL_1;

	case PP_DAL_POWERLEVEL_2:

		return DM_PP_CLOCKS_DPM_STATE_LEVEL_2;

	case PP_DAL_POWERLEVEL_3:

		return DM_PP_CLOCKS_DPM_STATE_LEVEL_3;

	case PP_DAL_POWERLEVEL_4:

		return DM_PP_CLOCKS_DPM_STATE_LEVEL_4;

	case PP_DAL_POWERLEVEL_5:

		return DM_PP_CLOCKS_DPM_STATE_LEVEL_5;

	case PP_DAL_POWERLEVEL_6:

		return DM_PP_CLOCKS_DPM_STATE_LEVEL_6;

	case PP_DAL_POWERLEVEL_7:

		return DM_PP_CLOCKS_DPM_STATE_LEVEL_7;

	default:

		DRM_ERROR("DM_PPLIB: invalid powerlevel state: %d!\n",

				max_clocks_state);

		return DM_PP_CLOCKS_STATE_INVALID;

	}

}



static void pp_to_dc_clock_levels(

		const struct amd_pp_clocks *pp_clks,

		struct dm_pp_clock_levels *dc_clks,
@@ -441,7 +468,7 @@ bool dm_pp_get_static_clocks( 
	if (ret)

		return false;



	static_clk_info->max_clocks_state = pp_clk_info.max_clocks_state;

	static_clk_info->max_clocks_state = pp_to_dc_powerlevel_state(pp_clk_info.max_clocks_state);

	static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock;

	static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock;