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Commit c2be369b authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "techpack: disp: pll: add support for dynamic refresh on DSI 14nm PLL"

parents 90cba358 6448a0ca

pll/dsi_pll_14nm.c

+8 −4
Original line number Diff line number Diff line
@@ -316,7 +316,8 @@ static struct clk_regmap_mux dsi0pll_pixel_clk_mux = { 
				(const char *[]){ "dsi0pll_pixel_clk_src",

					"dsi0pll_shadow_pixel_clk_src"},

			.num_parents = 2,

			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),

			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT |

					CLK_SET_RATE_NO_REPARENT),

			.ops = &clk_regmap_mux_closest_ops,

		},

	},
@@ -334,7 +335,8 @@ static struct clk_regmap_mux dsi1pll_pixel_clk_mux = { 
				(const char *[]){ "dsi1pll_pixel_clk_src",

					"dsi1pll_shadow_pixel_clk_src"},

			.num_parents = 2,

			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),

			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT |

					CLK_SET_RATE_NO_REPARENT),

			.ops = &clk_regmap_mux_closest_ops,

		},

	},
@@ -407,7 +409,8 @@ static struct clk_regmap_mux dsi0pll_byte_clk_mux = { 
					"dsi0pll_shadow_byte_clk_src"},

			.num_parents = 2,

			.ops = &clk_regmap_mux_closest_ops,

			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),

			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT |

					CLK_SET_RATE_NO_REPARENT),

		},

	},

};
@@ -425,7 +428,8 @@ static struct clk_regmap_mux dsi1pll_byte_clk_mux = { 
					"dsi1pll_shadow_byte_clk_src"},

			.num_parents = 2,

			.ops = &clk_regmap_mux_closest_ops,

			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),

			.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT |

					CLK_SET_RATE_NO_REPARENT),

		},

	},

};

pll/dsi_pll_14nm_util.c

+9 −3
Original line number Diff line number Diff line
@@ -38,9 +38,9 @@ static int mdss_pll_read_stored_trim_codes( 
		struct dfps_codes_info *codes_info =

			&dsi_pll_res->dfps->codes_dfps[i];



		pr_debug("valid=%d frame_rate=%d, code %d %d\n",

			codes_info->is_valid,

			codes_info->clk_rate, codes_info->pll_codes.pll_codes_1,

		pr_debug("valid=%d vco_rate=%d, code %d %d\n",

			codes_info->is_valid, codes_info->clk_rate,

			codes_info->pll_codes.pll_codes_1,

			codes_info->pll_codes.pll_codes_2);



		if (vco_clk_rate != codes_info->clk_rate &&
@@ -946,7 +946,13 @@ static void shadow_pll_dynamic_refresh_14nm(struct mdss_pll_resources *pll, 
							struct dsi_pll_db *pdb)

{

	struct dsi_pll_output *pout = &pdb->out;

	u32 data = 0;



	data = (pout->pll_n1div | (pout->pll_n2div << 4));

	MDSS_DYN_PLL_REG_W(pll->dyn_pll_base,

		DSI_DYNAMIC_REFRESH_PLL_CTRL19,

		DSIPHY_CMN_CLK_CFG0, DSIPHY_CMN_CLK_CFG1,

		data, 1);

	MDSS_DYN_PLL_REG_W(pll->dyn_pll_base,

		DSI_DYNAMIC_REFRESH_PLL_CTRL20,

		DSIPHY_CMN_CTRL_0, DSIPHY_PLL_SYSCLK_EN_RESET,