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Commit c2bc2fc5 authored by Imre Deak's avatar Imre Deak Committed by Daniel Vetter
Browse files

drm/i915: factor out gen6_update_ring_freq 



This is needed by the next patch moving the call out from platform
specific RPM callbacks to platform independent code.

No functional change.

v2:
- patch introduce in v2 of the patchset
v3:
- simplify platform check condition (Ville)

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent b5478bcd

drivers/gpu/drm/i915/i915_drv.c

+0 −2
Original line number Diff line number Diff line
@@ -927,9 +927,7 @@ static void snb_runtime_resume(struct drm_i915_private *dev_priv) 


	intel_init_pch_refclk(dev);

	i915_gem_init_swizzling(dev);

	mutex_lock(&dev_priv->rps.hw_lock);

	gen6_update_ring_freq(dev);

	mutex_unlock(&dev_priv->rps.hw_lock);

}



static void hsw_runtime_resume(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/intel_display.c

+0 −2
Original line number Diff line number Diff line
@@ -7057,9 +7057,7 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv) 


	intel_prepare_ddi(dev);

	i915_gem_init_swizzling(dev);

	mutex_lock(&dev_priv->rps.hw_lock);

	gen6_update_ring_freq(dev);

	mutex_unlock(&dev_priv->rps.hw_lock);

}



static void snb_modeset_global_resources(struct drm_device *dev)

drivers/gpu/drm/i915/intel_pm.c

+15 −3
Original line number Diff line number Diff line
@@ -3525,7 +3525,7 @@ static void gen6_enable_rps(struct drm_device *dev) 
	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);

}



void gen6_update_ring_freq(struct drm_device *dev)

static void __gen6_update_ring_freq(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int min_freq = 15;
@@ -3595,6 +3595,18 @@ void gen6_update_ring_freq(struct drm_device *dev) 
	}

}



void gen6_update_ring_freq(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))

		return;



	mutex_lock(&dev_priv->rps.hw_lock);

	__gen6_update_ring_freq(dev);

	mutex_unlock(&dev_priv->rps.hw_lock);

}



int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)

{

	u32 val, rp0;
@@ -4566,10 +4578,10 @@ static void intel_gen6_powersave_work(struct work_struct *work) 
		valleyview_enable_rps(dev);

	} else if (IS_BROADWELL(dev)) {

		gen8_enable_rps(dev);

		gen6_update_ring_freq(dev);

		__gen6_update_ring_freq(dev);

	} else {

		gen6_enable_rps(dev);

		gen6_update_ring_freq(dev);

		__gen6_update_ring_freq(dev);

	}

	dev_priv->rps.enabled = true;

	mutex_unlock(&dev_priv->rps.hw_lock);