Loading include/soc/swr-wcd.h +3 −1 Original line number Diff line number Diff line Loading @@ -32,8 +32,10 @@ struct swr_mstr_port { }; #define MCLK_FREQ 9600000 #define MCLK_FREQ_LP 600000 #define MCLK_FREQ_LP 4800000 #define MCLK_FREQ_NATIVE 11289600 #define MCLK_FREQ_ULP1 1200000 #define MCLK_FREQ_ULP2 600000 #if (IS_ENABLED(CONFIG_SOUNDWIRE_WCD_CTRL) || \ IS_ENABLED(CONFIG_SOUNDWIRE_MSTR_CTRL)) Loading soc/swr-mstr-ctrl.c +6 −3 Original line number Diff line number Diff line Loading @@ -1296,9 +1296,12 @@ static void swrm_apply_port_config(struct swr_master *master) dev_dbg(swrm->dev, "%s: enter bank: %d master_ports: %d\n", __func__, bank, master->num_port); if (bank == 0) swrm_cmd_fifo_wr_cmd(swrm, 0x01, 0xF, 0x00, SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(bank)); else swrm_cmd_fifo_wr_cmd(swrm, 0x00, 0xF, 0x00, SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(bank)); swrm_copy_data_port_config(master, bank); } Loading Loading
include/soc/swr-wcd.h +3 −1 Original line number Diff line number Diff line Loading @@ -32,8 +32,10 @@ struct swr_mstr_port { }; #define MCLK_FREQ 9600000 #define MCLK_FREQ_LP 600000 #define MCLK_FREQ_LP 4800000 #define MCLK_FREQ_NATIVE 11289600 #define MCLK_FREQ_ULP1 1200000 #define MCLK_FREQ_ULP2 600000 #if (IS_ENABLED(CONFIG_SOUNDWIRE_WCD_CTRL) || \ IS_ENABLED(CONFIG_SOUNDWIRE_MSTR_CTRL)) Loading
soc/swr-mstr-ctrl.c +6 −3 Original line number Diff line number Diff line Loading @@ -1296,9 +1296,12 @@ static void swrm_apply_port_config(struct swr_master *master) dev_dbg(swrm->dev, "%s: enter bank: %d master_ports: %d\n", __func__, bank, master->num_port); if (bank == 0) swrm_cmd_fifo_wr_cmd(swrm, 0x01, 0xF, 0x00, SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(bank)); else swrm_cmd_fifo_wr_cmd(swrm, 0x00, 0xF, 0x00, SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(bank)); swrm_copy_data_port_config(master, bank); } Loading