Loading Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt +2 −2 Original line number Diff line number Diff line Loading @@ -47,8 +47,8 @@ When the OS is not in control of the management interface (i.e. it's a guest), the channel nodes appear on their own, not under a management node. Required properties: - compatible: must contain "qcom,hidma-1.0" for initial HW or "qcom,hidma-1.1" for MSI capable HW. - compatible: must contain "qcom,hidma-1.0" for initial HW or "qcom,hidma-1.1"/"qcom,hidma-1.2" for MSI capable HW. - reg: Addresses for the transfer and event channel - interrupts: Should contain the event interrupt - desc-count: Number of asynchronous requests this channel can handle Loading drivers/dma/qcom/hidma.c +19 −22 Original line number Diff line number Diff line Loading @@ -50,6 +50,7 @@ #include <linux/slab.h> #include <linux/spinlock.h> #include <linux/of_dma.h> #include <linux/of_device.h> #include <linux/property.h> #include <linux/delay.h> #include <linux/acpi.h> Loading Loading @@ -104,6 +105,10 @@ static unsigned int nr_desc_prm; module_param(nr_desc_prm, uint, 0644); MODULE_PARM_DESC(nr_desc_prm, "number of descriptors (default: 0)"); enum hidma_cap { HIDMA_MSI_CAP = 1, HIDMA_IDENTITY_CAP, }; /* process completed descriptors */ static void hidma_process_completed(struct hidma_chan *mchan) Loading Loading @@ -736,25 +741,12 @@ static int hidma_request_msi(struct hidma_dev *dmadev, #endif } static bool hidma_msi_capable(struct device *dev) static bool hidma_test_capability(struct device *dev, enum hidma_cap test_cap) { struct acpi_device *adev = ACPI_COMPANION(dev); const char *of_compat; int ret = -EINVAL; if (!adev || acpi_disabled) { ret = device_property_read_string(dev, "compatible", &of_compat); if (ret) return false; enum hidma_cap cap; ret = strcmp(of_compat, "qcom,hidma-1.1"); } else { #ifdef CONFIG_ACPI ret = strcmp(acpi_device_hid(adev), "QCOM8062"); #endif } return ret == 0; cap = (enum hidma_cap) device_get_match_data(dev); return cap ? ((cap & test_cap) > 0) : 0; } static int hidma_probe(struct platform_device *pdev) Loading Loading @@ -834,8 +826,7 @@ static int hidma_probe(struct platform_device *pdev) * Determine the MSI capability of the platform. Old HW doesn't * support MSI. */ msi = hidma_msi_capable(&pdev->dev); msi = hidma_test_capability(&pdev->dev, HIDMA_MSI_CAP); device_property_read_u32(&pdev->dev, "desc-count", &dmadev->nr_descriptors); Loading @@ -848,6 +839,9 @@ static int hidma_probe(struct platform_device *pdev) if (!dmadev->nr_descriptors) dmadev->nr_descriptors = HIDMA_NR_DEFAULT_DESC; if (hidma_test_capability(&pdev->dev, HIDMA_IDENTITY_CAP)) dmadev->chidx = readl(dmadev->dev_trca + 0x40); else dmadev->chidx = readl(dmadev->dev_trca + 0x28); /* Set DMA mask to 64 bits. */ Loading Loading @@ -953,7 +947,8 @@ static int hidma_remove(struct platform_device *pdev) #if IS_ENABLED(CONFIG_ACPI) static const struct acpi_device_id hidma_acpi_ids[] = { {"QCOM8061"}, {"QCOM8062"}, {"QCOM8062", HIDMA_MSI_CAP}, {"QCOM8063", (HIDMA_MSI_CAP | HIDMA_IDENTITY_CAP)}, {}, }; MODULE_DEVICE_TABLE(acpi, hidma_acpi_ids); Loading @@ -961,7 +956,9 @@ MODULE_DEVICE_TABLE(acpi, hidma_acpi_ids); static const struct of_device_id hidma_match[] = { {.compatible = "qcom,hidma-1.0",}, {.compatible = "qcom,hidma-1.1",}, {.compatible = "qcom,hidma-1.1", .data = (void *)(HIDMA_MSI_CAP),}, {.compatible = "qcom,hidma-1.2", .data = (void *)(HIDMA_MSI_CAP | HIDMA_IDENTITY_CAP),}, {}, }; MODULE_DEVICE_TABLE(of, hidma_match); Loading drivers/dma/qcom/hidma_ll.c +6 −3 Original line number Diff line number Diff line Loading @@ -393,6 +393,8 @@ static int hidma_ll_reset(struct hidma_lldev *lldev) */ static void hidma_ll_int_handler_internal(struct hidma_lldev *lldev, int cause) { unsigned long irqflags; if (cause & HIDMA_ERR_INT_MASK) { dev_err(lldev->dev, "error 0x%x, disabling...\n", cause); Loading @@ -410,6 +412,10 @@ static void hidma_ll_int_handler_internal(struct hidma_lldev *lldev, int cause) return; } spin_lock_irqsave(&lldev->lock, irqflags); writel_relaxed(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG); spin_unlock_irqrestore(&lldev->lock, irqflags); /* * Fine tuned for this HW... * Loading @@ -421,9 +427,6 @@ static void hidma_ll_int_handler_internal(struct hidma_lldev *lldev, int cause) * Try to consume as many EVREs as possible. */ hidma_handle_tre_completion(lldev); /* We consumed TREs or there are pending TREs or EVREs. */ writel_relaxed(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG); } irqreturn_t hidma_ll_inthandler(int chirq, void *arg) Loading Loading
Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt +2 −2 Original line number Diff line number Diff line Loading @@ -47,8 +47,8 @@ When the OS is not in control of the management interface (i.e. it's a guest), the channel nodes appear on their own, not under a management node. Required properties: - compatible: must contain "qcom,hidma-1.0" for initial HW or "qcom,hidma-1.1" for MSI capable HW. - compatible: must contain "qcom,hidma-1.0" for initial HW or "qcom,hidma-1.1"/"qcom,hidma-1.2" for MSI capable HW. - reg: Addresses for the transfer and event channel - interrupts: Should contain the event interrupt - desc-count: Number of asynchronous requests this channel can handle Loading
drivers/dma/qcom/hidma.c +19 −22 Original line number Diff line number Diff line Loading @@ -50,6 +50,7 @@ #include <linux/slab.h> #include <linux/spinlock.h> #include <linux/of_dma.h> #include <linux/of_device.h> #include <linux/property.h> #include <linux/delay.h> #include <linux/acpi.h> Loading Loading @@ -104,6 +105,10 @@ static unsigned int nr_desc_prm; module_param(nr_desc_prm, uint, 0644); MODULE_PARM_DESC(nr_desc_prm, "number of descriptors (default: 0)"); enum hidma_cap { HIDMA_MSI_CAP = 1, HIDMA_IDENTITY_CAP, }; /* process completed descriptors */ static void hidma_process_completed(struct hidma_chan *mchan) Loading Loading @@ -736,25 +741,12 @@ static int hidma_request_msi(struct hidma_dev *dmadev, #endif } static bool hidma_msi_capable(struct device *dev) static bool hidma_test_capability(struct device *dev, enum hidma_cap test_cap) { struct acpi_device *adev = ACPI_COMPANION(dev); const char *of_compat; int ret = -EINVAL; if (!adev || acpi_disabled) { ret = device_property_read_string(dev, "compatible", &of_compat); if (ret) return false; enum hidma_cap cap; ret = strcmp(of_compat, "qcom,hidma-1.1"); } else { #ifdef CONFIG_ACPI ret = strcmp(acpi_device_hid(adev), "QCOM8062"); #endif } return ret == 0; cap = (enum hidma_cap) device_get_match_data(dev); return cap ? ((cap & test_cap) > 0) : 0; } static int hidma_probe(struct platform_device *pdev) Loading Loading @@ -834,8 +826,7 @@ static int hidma_probe(struct platform_device *pdev) * Determine the MSI capability of the platform. Old HW doesn't * support MSI. */ msi = hidma_msi_capable(&pdev->dev); msi = hidma_test_capability(&pdev->dev, HIDMA_MSI_CAP); device_property_read_u32(&pdev->dev, "desc-count", &dmadev->nr_descriptors); Loading @@ -848,6 +839,9 @@ static int hidma_probe(struct platform_device *pdev) if (!dmadev->nr_descriptors) dmadev->nr_descriptors = HIDMA_NR_DEFAULT_DESC; if (hidma_test_capability(&pdev->dev, HIDMA_IDENTITY_CAP)) dmadev->chidx = readl(dmadev->dev_trca + 0x40); else dmadev->chidx = readl(dmadev->dev_trca + 0x28); /* Set DMA mask to 64 bits. */ Loading Loading @@ -953,7 +947,8 @@ static int hidma_remove(struct platform_device *pdev) #if IS_ENABLED(CONFIG_ACPI) static const struct acpi_device_id hidma_acpi_ids[] = { {"QCOM8061"}, {"QCOM8062"}, {"QCOM8062", HIDMA_MSI_CAP}, {"QCOM8063", (HIDMA_MSI_CAP | HIDMA_IDENTITY_CAP)}, {}, }; MODULE_DEVICE_TABLE(acpi, hidma_acpi_ids); Loading @@ -961,7 +956,9 @@ MODULE_DEVICE_TABLE(acpi, hidma_acpi_ids); static const struct of_device_id hidma_match[] = { {.compatible = "qcom,hidma-1.0",}, {.compatible = "qcom,hidma-1.1",}, {.compatible = "qcom,hidma-1.1", .data = (void *)(HIDMA_MSI_CAP),}, {.compatible = "qcom,hidma-1.2", .data = (void *)(HIDMA_MSI_CAP | HIDMA_IDENTITY_CAP),}, {}, }; MODULE_DEVICE_TABLE(of, hidma_match); Loading
drivers/dma/qcom/hidma_ll.c +6 −3 Original line number Diff line number Diff line Loading @@ -393,6 +393,8 @@ static int hidma_ll_reset(struct hidma_lldev *lldev) */ static void hidma_ll_int_handler_internal(struct hidma_lldev *lldev, int cause) { unsigned long irqflags; if (cause & HIDMA_ERR_INT_MASK) { dev_err(lldev->dev, "error 0x%x, disabling...\n", cause); Loading @@ -410,6 +412,10 @@ static void hidma_ll_int_handler_internal(struct hidma_lldev *lldev, int cause) return; } spin_lock_irqsave(&lldev->lock, irqflags); writel_relaxed(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG); spin_unlock_irqrestore(&lldev->lock, irqflags); /* * Fine tuned for this HW... * Loading @@ -421,9 +427,6 @@ static void hidma_ll_int_handler_internal(struct hidma_lldev *lldev, int cause) * Try to consume as many EVREs as possible. */ hidma_handle_tre_completion(lldev); /* We consumed TREs or there are pending TREs or EVREs. */ writel_relaxed(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG); } irqreturn_t hidma_ll_inthandler(int chirq, void *arg) Loading