Loading include/dt-bindings/clock/rk3188-cru-common.h +7 −2 Original line number Diff line number Diff line Loading @@ -68,12 +68,14 @@ #define ACLK_LCDC1 196 #define ACLK_GPU 197 #define ACLK_SMC 198 #define ACLK_CIF 199 #define ACLK_CIF1 199 #define ACLK_IPP 200 #define ACLK_RGA 201 #define ACLK_CIF0 202 #define ACLK_CPU 203 #define ACLK_PERI 204 #define ACLK_VEPU 205 #define ACLK_VDPU 206 /* pclk gates */ #define PCLK_GRF 320 Loading Loading @@ -134,8 +136,11 @@ #define HCLK_NANDC0 467 #define HCLK_CPU 468 #define HCLK_PERI 469 #define HCLK_CIF1 470 #define HCLK_VEPU 471 #define HCLK_VDPU 472 #define CLK_NR_CLKS (HCLK_PERI + 1) #define CLK_NR_CLKS (HCLK_VDPU + 1) /* soft-reset indices */ #define SRST_MCORE 2 Loading include/dt-bindings/clock/rk3368-cru.h +1 −0 Original line number Diff line number Diff line Loading @@ -156,6 +156,7 @@ #define PCLK_ISP 366 #define PCLK_VIP 367 #define PCLK_WDT 368 #define PCLK_EFUSE256 369 /* hclk gates */ #define HCLK_SFC 448 Loading Loading
include/dt-bindings/clock/rk3188-cru-common.h +7 −2 Original line number Diff line number Diff line Loading @@ -68,12 +68,14 @@ #define ACLK_LCDC1 196 #define ACLK_GPU 197 #define ACLK_SMC 198 #define ACLK_CIF 199 #define ACLK_CIF1 199 #define ACLK_IPP 200 #define ACLK_RGA 201 #define ACLK_CIF0 202 #define ACLK_CPU 203 #define ACLK_PERI 204 #define ACLK_VEPU 205 #define ACLK_VDPU 206 /* pclk gates */ #define PCLK_GRF 320 Loading Loading @@ -134,8 +136,11 @@ #define HCLK_NANDC0 467 #define HCLK_CPU 468 #define HCLK_PERI 469 #define HCLK_CIF1 470 #define HCLK_VEPU 471 #define HCLK_VDPU 472 #define CLK_NR_CLKS (HCLK_PERI + 1) #define CLK_NR_CLKS (HCLK_VDPU + 1) /* soft-reset indices */ #define SRST_MCORE 2 Loading
include/dt-bindings/clock/rk3368-cru.h +1 −0 Original line number Diff line number Diff line Loading @@ -156,6 +156,7 @@ #define PCLK_ISP 366 #define PCLK_VIP 367 #define PCLK_WDT 368 #define PCLK_EFUSE256 369 /* hclk gates */ #define HCLK_SFC 448 Loading