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Commit c1b51124 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-3.6' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 

Alex writes:

Highlights:
- fix a gart regression on older IGP chips
- more MSAA fixes
- fix a double free in gpu reset code
- modesetting fixes
- trinity dig encoder fix.

* 'drm-fixes-3.6' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: fix dig encoder selection on DCE61
  drm/radeon: fix double free in radeon_gpu_reset
  drm/radeon: force dma32 to fix regression rs4xx,rs6xx,rs740
  drm/radeon: rework panel mode setup
  drm/radeon/atom: powergating fixes for DCE6
  drm/radeon/atom: rework DIG modesetting on DCE3+
  drm/radeon: don't disable plls that are in use by other crtcs
  drm/radeon: add proper checking of RESOLVE_BOX command for r600-r700
  drm/radeon: initialize tracked CS state
  drm/radeon: fix reading CB_COLORn_MASK from the CS
parents 4a68a74b 41fa5437

drivers/gpu/drm/radeon/atombios_crtc.c

+16 −20
Original line number Diff line number Diff line
@@ -258,7 +258,6 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 
		radeon_crtc->enabled = true;

		/* adjust pm to dpms changes BEFORE enabling crtcs */

		radeon_pm_compute_clocks(rdev);

		/* disable crtc pair power gating before programming */

		if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)

			atombios_powergate_crtc(crtc, ATOM_DISABLE);

		atombios_enable_crtc(crtc, ATOM_ENABLE);
@@ -278,25 +277,8 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 
			atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);

		atombios_enable_crtc(crtc, ATOM_DISABLE);

		radeon_crtc->enabled = false;

		/* power gating is per-pair */

		if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) {

			struct drm_crtc *other_crtc;

			struct radeon_crtc *other_radeon_crtc;

			list_for_each_entry(other_crtc, &rdev->ddev->mode_config.crtc_list, head) {

				other_radeon_crtc = to_radeon_crtc(other_crtc);

				if (((radeon_crtc->crtc_id == 0) && (other_radeon_crtc->crtc_id == 1)) ||

				    ((radeon_crtc->crtc_id == 1) && (other_radeon_crtc->crtc_id == 0)) ||

				    ((radeon_crtc->crtc_id == 2) && (other_radeon_crtc->crtc_id == 3)) ||

				    ((radeon_crtc->crtc_id == 3) && (other_radeon_crtc->crtc_id == 2)) ||

				    ((radeon_crtc->crtc_id == 4) && (other_radeon_crtc->crtc_id == 5)) ||

				    ((radeon_crtc->crtc_id == 5) && (other_radeon_crtc->crtc_id == 4))) {

					/* if both crtcs in the pair are off, enable power gating */

					if (other_radeon_crtc->enabled == false)

		if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)

			atombios_powergate_crtc(crtc, ATOM_ENABLE);

					break;

				}

			}

		}

		/* adjust pm to dpms changes AFTER disabling crtcs */

		radeon_pm_compute_clocks(rdev);

		break;
@@ -1682,9 +1664,22 @@ static void atombios_crtc_disable(struct drm_crtc *crtc) 
	struct drm_device *dev = crtc->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_atom_ss ss;

	int i;



	atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);



	for (i = 0; i < rdev->num_crtc; i++) {

		if (rdev->mode_info.crtcs[i] &&

		    rdev->mode_info.crtcs[i]->enabled &&

		    i != radeon_crtc->crtc_id &&

		    radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {

			/* one other crtc is using this pll don't turn

			 * off the pll

			 */

			goto done;

		}

	}



	switch (radeon_crtc->pll_id) {

	case ATOM_PPLL1:

	case ATOM_PPLL2:
@@ -1701,6 +1696,7 @@ static void atombios_crtc_disable(struct drm_crtc *crtc) 
	default:

		break;

	}

done:

	radeon_crtc->pll_id = -1;

}

drivers/gpu/drm/radeon/atombios_dp.c

+12 −17
Original line number Diff line number Diff line
@@ -577,30 +577,25 @@ int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 
	struct radeon_device *rdev = dev->dev_private;

	struct radeon_connector *radeon_connector = to_radeon_connector(connector);

	int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;

	u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);

	u8 tmp;



	if (!ASIC_IS_DCE4(rdev))

		return panel_mode;



	if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==

	    ENCODER_OBJECT_ID_NUTMEG)

		panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;

	else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==

		 ENCODER_OBJECT_ID_TRAVIS) {

		u8 id[6];

		int i;

		for (i = 0; i < 6; i++)

			id[i] = radeon_read_dpcd_reg(radeon_connector, 0x503 + i);

		if (id[0] == 0x73 &&

		    id[1] == 0x69 &&

		    id[2] == 0x76 &&

		    id[3] == 0x61 &&

		    id[4] == 0x72 &&

		    id[5] == 0x54)

	if (dp_bridge != ENCODER_OBJECT_ID_NONE) {

		/* DP bridge chips */

		tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);

		if (tmp & 1)

			panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;

		else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||

			 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))

			panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;

		else

			panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;

			panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;

	} else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {

		u8 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);

		/* eDP */

		tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);

		if (tmp & 1)

			panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;

	}

drivers/gpu/drm/radeon/atombios_encoders.c

+73 −67
Original line number Diff line number Diff line
@@ -1379,6 +1379,8 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 
	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);

	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);

	struct radeon_connector *radeon_connector = NULL;

	struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
@@ -1390,18 +1392,36 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 


	switch (mode) {

	case DRM_MODE_DPMS_ON:

		/* some early dce3.2 boards have a bug in their transmitter control table */

		if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730) ||

		    ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {

			if (ASIC_IS_DCE6(rdev)) {

				/* It seems we need to call ATOM_ENCODER_CMD_SETUP again

				 * before reenabling encoder on DPMS ON, otherwise we never

				 * get picture

				 */

		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {

			if (!connector)

				dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;

			else

				dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);



			/* setup and enable the encoder */

			atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);

			atombios_dig_encoder_setup(encoder,

						   ATOM_ENCODER_CMD_SETUP_PANEL_MODE,

						   dig->panel_mode);

			if (ext_encoder) {

				if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))

					atombios_external_encoder_setup(encoder, ext_encoder,

									EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);

			}

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);

		} else if (ASIC_IS_DCE4(rdev)) {

			/* setup and enable the encoder */

			atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);

			/* enable the transmitter */

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);

		} else {

			/* setup and enable the encoder and transmitter */

			atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);

			/* some early dce3.2 boards have a bug in their transmitter control table */

			if ((rdev->family != CHIP_RV710) || (rdev->family != CHIP_RV730))

				atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);

		}

		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
@@ -1420,10 +1440,19 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 
	case DRM_MODE_DPMS_STANDBY:

	case DRM_MODE_DPMS_SUSPEND:

	case DRM_MODE_DPMS_OFF:

		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev))

		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {

			/* disable the transmitter */

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);

		else

		} else if (ASIC_IS_DCE4(rdev)) {

			/* disable the transmitter */

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);

		} else {

			/* disable the encoder and transmitter */

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);

			atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);

		}

		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {

			if (ASIC_IS_DCE4(rdev))

				atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
@@ -1740,13 +1769,34 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) 
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct drm_encoder *test_encoder;

	struct radeon_encoder_atom_dig *dig;

	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	uint32_t dig_enc_in_use = 0;



	if (ASIC_IS_DCE6(rdev)) {

		/* DCE6 */

		switch (radeon_encoder->encoder_id) {

		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:

			if (dig->linkb)

				return 1;

			else

				return 0;

			break;

		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:

			if (dig->linkb)

				return 3;

			else

				return 2;

			break;

		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:

			if (dig->linkb)

				return 5;

			else

				return 4;

			break;

		}

	} else if (ASIC_IS_DCE4(rdev)) {

		/* DCE4/5 */

	if (ASIC_IS_DCE4(rdev)) {

		dig = radeon_encoder->enc_priv;

		if (ASIC_IS_DCE41(rdev)) {

		if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {

			/* ontario follows DCE4 */

			if (rdev->family == CHIP_PALM) {

				if (dig->linkb)
@@ -1848,10 +1898,12 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 
	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);



	radeon_encoder->pixel_clock = adjusted_mode->clock;



	/* need to call this here rather than in prepare() since we need some crtc info */

	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);



	if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {

		if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))

			atombios_yuv_setup(encoder, true);
@@ -1870,38 +1922,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:

	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:

		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {

			struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);

			struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;



			if (!connector)

				dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;

			else

				dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);



			/* setup and enable the encoder */

			atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);

			atombios_dig_encoder_setup(encoder,

						   ATOM_ENCODER_CMD_SETUP_PANEL_MODE,

						   dig->panel_mode);

		} else if (ASIC_IS_DCE4(rdev)) {

			/* disable the transmitter */

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);

			/* setup and enable the encoder */

			atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);



			/* enable the transmitter */

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);

		} else {

			/* disable the encoder and transmitter */

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);

			atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);



			/* setup and enable the encoder and transmitter */

			atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);

		}

		/* handled in dpms */

		break;

	case ENCODER_OBJECT_ID_INTERNAL_DDI:

	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
@@ -1922,14 +1943,6 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 
		break;

	}



	if (ext_encoder) {

		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))

			atombios_external_encoder_setup(encoder, ext_encoder,

							EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);

		else

			atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);

	}



	atombios_apply_encoder_quirks(encoder, adjusted_mode);



	if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
@@ -2116,7 +2129,6 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 
	}



	radeon_atom_output_lock(encoder, true);

	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);



	if (connector) {

		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
@@ -2137,6 +2149,7 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 


static void radeon_atom_encoder_commit(struct drm_encoder *encoder)

{

	/* need to call this here as we need the crtc set up */

	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);

	radeon_atom_output_lock(encoder, false);

}
@@ -2177,14 +2190,7 @@ static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 
	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:

	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:

		if (ASIC_IS_DCE4(rdev))

			/* disable the transmitter */

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);

		else {

			/* disable the encoder and transmitter */

			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);

			atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);

		}

		/* handled in dpms */

		break;

	case ENCODER_OBJECT_ID_INTERNAL_DDI:

	case ENCODER_OBJECT_ID_INTERNAL_DVO1:

drivers/gpu/drm/radeon/r600_cs.c

+26 −4
Original line number Diff line number Diff line
@@ -63,6 +63,7 @@ struct r600_cs_track { 
	u32			cb_color_size_idx[8]; /* unused */

	u32			cb_target_mask;

	u32			cb_shader_mask;  /* unused */

	bool			is_resolve;

	u32			cb_color_size[8];

	u32			vgt_strmout_en;

	u32			vgt_strmout_buffer_en;
@@ -315,7 +316,15 @@ static void r600_cs_track_init(struct r600_cs_track *track) 
		track->cb_color_bo[i] = NULL;

		track->cb_color_bo_offset[i] = 0xFFFFFFFF;

		track->cb_color_bo_mc[i] = 0xFFFFFFFF;

	}

		track->cb_color_frag_bo[i] = NULL;

		track->cb_color_frag_offset[i] = 0xFFFFFFFF;

		track->cb_color_tile_bo[i] = NULL;

		track->cb_color_tile_offset[i] = 0xFFFFFFFF;

		track->cb_color_mask[i] = 0xFFFFFFFF;

	}

	track->is_resolve = false;

	track->nsamples = 16;

	track->log_nsamples = 4;

	track->cb_target_mask = 0xFFFFFFFF;

	track->cb_shader_mask = 0xFFFFFFFF;

	track->cb_dirty = true;
@@ -352,6 +361,8 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) 
	volatile u32 *ib = p->ib.ptr;

	unsigned array_mode;

	u32 format;

	/* When resolve is used, the second colorbuffer has always 1 sample. */

	unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples;



	size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];

	format = G_0280A0_FORMAT(track->cb_color_info[i]);
@@ -375,7 +386,7 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) 
	array_check.group_size = track->group_size;

	array_check.nbanks = track->nbanks;

	array_check.npipes = track->npipes;

	array_check.nsamples = track->nsamples;

	array_check.nsamples = nsamples;

	array_check.blocksize = r600_fmt_get_blocksize(format);

	if (r600_get_array_mode_alignment(&array_check,

					  &pitch_align, &height_align, &depth_align, &base_align)) {
@@ -421,7 +432,7 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) 


	/* check offset */

	tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *

	      r600_fmt_get_blocksize(format) * track->nsamples;

	      r600_fmt_get_blocksize(format) * nsamples;

	switch (array_mode) {

	default:

	case V_0280A0_ARRAY_LINEAR_GENERAL:
@@ -792,6 +803,12 @@ static int r600_cs_track_check(struct radeon_cs_parser *p) 
	 */

	if (track->cb_dirty) {

		tmp = track->cb_target_mask;



		/* We must check both colorbuffers for RESOLVE. */

		if (track->is_resolve) {

			tmp |= 0xff;

		}



		for (i = 0; i < 8; i++) {

			if ((tmp >> (i * 4)) & 0xF) {

				/* at least one component is enabled */
@@ -1281,6 +1298,11 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 
		track->nsamples = 1 << tmp;

		track->cb_dirty = true;

		break;

	case R_028808_CB_COLOR_CONTROL:

		tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));

		track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;

		track->cb_dirty = true;

		break;

	case R_0280A0_CB_COLOR0_INFO:

	case R_0280A4_CB_COLOR1_INFO:

	case R_0280A8_CB_COLOR2_INFO:
@@ -1416,7 +1438,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 
	case R_028118_CB_COLOR6_MASK:

	case R_02811C_CB_COLOR7_MASK:

		tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;

		track->cb_color_mask[tmp] = ib[idx];

		track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);

		if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {

			track->cb_dirty = true;

		}

drivers/gpu/drm/radeon/r600d.h

+8 −0
Original line number Diff line number Diff line
@@ -66,6 +66,14 @@ 
#define	CC_RB_BACKEND_DISABLE				0x98F4

#define		BACKEND_DISABLE(x)				((x) << 16)



#define R_028808_CB_COLOR_CONTROL			0x28808

#define   S_028808_SPECIAL_OP(x)                       (((x) & 0x7) << 4)

#define   G_028808_SPECIAL_OP(x)                       (((x) >> 4) & 0x7)

#define   C_028808_SPECIAL_OP                          0xFFFFFF8F

#define     V_028808_SPECIAL_NORMAL                     0x00

#define     V_028808_SPECIAL_DISABLE                    0x01

#define     V_028808_SPECIAL_RESOLVE_BOX                0x07



#define	CB_COLOR0_BASE					0x28040

#define	CB_COLOR1_BASE					0x28044

#define	CB_COLOR2_BASE					0x28048