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Commit c14038c3 authored by David Howells's avatar David Howells Committed by Linus Torvalds
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[PATCH] Improve data-dependency memory barrier example in documentation 



In the memory barrier document, improve the example of the data dependency
barrier situation by:

 (1) showing the initial values of the variables involved; and

 (2) repeating the instruction sequence description, this time with the data
     dependency barrier actually shown to make it clear what the revised
     sequence actually is.

Signed-off-by: default avatarDavid Howells <dhowells@redhat.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent dbc8700e

Documentation/memory-barriers.txt

+15 −1
Original line number Diff line number Diff line
@@ -610,6 +610,7 @@ loads. Consider the following sequence of events: 


	CPU 1			CPU 2

	=======================	=======================

		{ B = 7; X = 9; Y = 8; C = &Y }

	STORE A = 1

	STORE B = 2

	<write barrier>
@@ -651,7 +652,20 @@ In the above example, CPU 2 perceives that B is 7, despite the load of *C 
(which would be B) coming after the the LOAD of C.



If, however, a data dependency barrier were to be placed between the load of C

and the load of *C (ie: B) on CPU 2, then the following will occur:

and the load of *C (ie: B) on CPU 2:



	CPU 1			CPU 2

	=======================	=======================

		{ B = 7; X = 9; Y = 8; C = &Y }

	STORE A = 1

	STORE B = 2

	<write barrier>

	STORE C = &B		LOAD X

	STORE D = 4		LOAD C (gets &B)

				<data dependency barrier>

				LOAD *C (reads B)



then the following will occur:



	+-------+       :      :                :       :

	|       |       +------+                +-------+