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Commit c131623b authored by Jeremy Linton's avatar Jeremy Linton Committed by Greg Kroah-Hartman
Browse files

arm64: Always enable ssb vulnerability detection 



[ Upstream commit d42281b6e49510f078ace15a8ea10f71e6262581 ]

Ensure we are always able to detect whether or not the CPU is affected
by SSB, so that we can later advertise this to userspace.

Signed-off-by: default avatarJeremy Linton <jeremy.linton@arm.com>
Reviewed-by: default avatarAndre Przywara <andre.przywara@arm.com>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Tested-by: default avatarStefan Wahren <stefan.wahren@i2se.com>
[will: Use IS_ENABLED instead of #ifdef]
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 47a11f2e

arch/arm64/include/asm/cpufeature.h

+0 −4
Original line number Diff line number Diff line
@@ -525,11 +525,7 @@ static inline int arm64_get_ssbd_state(void) 
#endif

}



#ifdef CONFIG_ARM64_SSBD

void arm64_set_ssbd_mitigation(bool state);

#else

static inline void arm64_set_ssbd_mitigation(bool state) {}

#endif



#endif /* __ASSEMBLY__ */

arch/arm64/kernel/cpu_errata.c

+5 −4
Original line number Diff line number Diff line
@@ -239,7 +239,6 @@ enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry) 
}

#endif	/* CONFIG_HARDEN_BRANCH_PREDICTOR */



#ifdef CONFIG_ARM64_SSBD

DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required);



int ssbd_state __read_mostly = ARM64_SSBD_KERNEL;
@@ -312,6 +311,11 @@ void __init arm64_enable_wa2_handling(struct alt_instr *alt, 


void arm64_set_ssbd_mitigation(bool state)

{

	if (!IS_ENABLED(CONFIG_ARM64_SSBD)) {

		pr_info_once("SSBD disabled by kernel configuration\n");

		return;

	}



	if (this_cpu_has_cap(ARM64_SSBS)) {

		if (state)

			asm volatile(SET_PSTATE_SSBS(0));
@@ -431,7 +435,6 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, 


	return required;

}

#endif	/* CONFIG_ARM64_SSBD */



#ifdef CONFIG_ARM64_ERRATUM_1463225

DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
@@ -710,14 +713,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors),

	},

#endif

#ifdef CONFIG_ARM64_SSBD

	{

		.desc = "Speculative Store Bypass Disable",

		.capability = ARM64_SSBD,

		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,

		.matches = has_ssbd_mitigation,

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_1463225

	{

		.desc = "ARM erratum 1463225",