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Commit c08e20d2 authored by Dinh Nguyen's avatar Dinh Nguyen Committed by Olof Johansson
Browse files

arm: Add v7_invalidate_l1 to cache-v7.S 



mach-socfpga is another platform that needs to use
v7_invalidate_l1 to bringup additional cores. There was a comment that
the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S

Signed-off-by: default avatarDinh Nguyen <dinguyen@altera.com>
Acked-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Acked-by: default avatarStephen Warren <swarren@nvidia.com>
Reviewed-by: default avatarPavel Machek <pavel@denx.de>
Reviewed-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: default avatarPavel Machek <pavel@denx.de>
Tested-by: default avatarStephen Warren <swarren@nvidia.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Olof Johansson <olof@lixom.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Magnus Damm <magnus.damm@gmail.com>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 90c29455

arch/arm/mach-imx/headsmp.S

+0 −47
Original line number Original line Diff line number Diff line
@@ -17,53 +17,6 @@ 




	.section ".text.head", "ax"

	.section ".text.head", "ax"





/*

 * The secondary kernel init calls v7_flush_dcache_all before it enables

 * the L1; however, the L1 comes out of reset in an undefined state, so

 * the clean + invalidate performed by v7_flush_dcache_all causes a bunch

 * of cache lines with uninitialized data and uninitialized tags to get

 * written out to memory, which does really unpleasant things to the main

 * processor.  We fix this by performing an invalidate, rather than a

 * clean + invalidate, before jumping into the kernel.

 *

 * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs

 * to be called for both secondary cores startup and primary core resume

 * procedures.  Ideally, it should be moved into arch/arm/mm/cache-v7.S.

 */

ENTRY(v7_invalidate_l1)

	mov	r0, #0

	mcr	p15, 0, r0, c7, c5, 0	@ invalidate I cache

	mcr	p15, 2, r0, c0, c0, 0

	mrc	p15, 1, r0, c0, c0, 0



	ldr	r1, =0x7fff

	and	r2, r1, r0, lsr #13



	ldr	r1, =0x3ff



	and	r3, r1, r0, lsr #3	@ NumWays - 1

	add	r2, r2, #1		@ NumSets



	and	r0, r0, #0x7

	add	r0, r0, #4	@ SetShift



	clz	r1, r3		@ WayShift

	add	r4, r3, #1	@ NumWays

1:	sub	r2, r2, #1	@ NumSets--

	mov	r3, r4		@ Temp = NumWays

2:	subs	r3, r3, #1	@ Temp--

	mov	r5, r3, lsl r1

	mov	r6, r2, lsl r0

	orr	r5, r5, r6	@ Reg = (Temp<<WayShift)|(NumSets<<SetShift)

	mcr	p15, 0, r5, c7, c6, 2

	bgt	2b

	cmp	r2, #0

	bgt	1b

	dsb

	isb

	mov	pc, lr

ENDPROC(v7_invalidate_l1)



#ifdef CONFIG_SMP

#ifdef CONFIG_SMP

ENTRY(v7_secondary_startup)

ENTRY(v7_secondary_startup)

	bl	v7_invalidate_l1

	bl	v7_invalidate_l1

arch/arm/mach-shmobile/headsmp.S

+0 −48
Original line number Original line Diff line number Diff line
@@ -16,54 +16,6 @@ 




	__CPUINIT

	__CPUINIT





/* Cache invalidation nicked from arch/arm/mach-imx/head-v7.S, thanks!

 *

 * The secondary kernel init calls v7_flush_dcache_all before it enables

 * the L1; however, the L1 comes out of reset in an undefined state, so

 * the clean + invalidate performed by v7_flush_dcache_all causes a bunch

 * of cache lines with uninitialized data and uninitialized tags to get

 * written out to memory, which does really unpleasant things to the main

 * processor.  We fix this by performing an invalidate, rather than a

 * clean + invalidate, before jumping into the kernel.

 *

 * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs

 * to be called for both secondary cores startup and primary core resume

 * procedures.  Ideally, it should be moved into arch/arm/mm/cache-v7.S.

 */

ENTRY(v7_invalidate_l1)

	mov	r0, #0

	mcr	p15, 0, r0, c7, c5, 0	@ invalidate I cache

	mcr	p15, 2, r0, c0, c0, 0

	mrc	p15, 1, r0, c0, c0, 0



	ldr	r1, =0x7fff

	and	r2, r1, r0, lsr #13



	ldr	r1, =0x3ff



	and	r3, r1, r0, lsr #3	@ NumWays - 1

	add	r2, r2, #1		@ NumSets



	and	r0, r0, #0x7

	add	r0, r0, #4	@ SetShift



	clz	r1, r3		@ WayShift

	add	r4, r3, #1	@ NumWays

1:	sub	r2, r2, #1	@ NumSets--

	mov	r3, r4		@ Temp = NumWays

2:	subs	r3, r3, #1	@ Temp--

	mov	r5, r3, lsl r1

	mov	r6, r2, lsl r0

	orr	r5, r5, r6	@ Reg = (Temp<<WayShift)|(NumSets<<SetShift)

	mcr	p15, 0, r5, c7, c6, 2

	bgt	2b

	cmp	r2, #0

	bgt	1b

	dsb

	isb

	mov	pc, lr

ENDPROC(v7_invalidate_l1)



ENTRY(shmobile_invalidate_start)

ENTRY(shmobile_invalidate_start)

	bl	v7_invalidate_l1

	bl	v7_invalidate_l1

	b	secondary_startup

	b	secondary_startup

arch/arm/mach-tegra/headsmp.S

+0 −43
Original line number Original line Diff line number Diff line
@@ -18,49 +18,6 @@ 
        .section ".text.head", "ax"

        .section ".text.head", "ax"

	__CPUINIT

	__CPUINIT





/*

 * Tegra specific entry point for secondary CPUs.

 *   The secondary kernel init calls v7_flush_dcache_all before it enables

 *   the L1; however, the L1 comes out of reset in an undefined state, so

 *   the clean + invalidate performed by v7_flush_dcache_all causes a bunch

 *   of cache lines with uninitialized data and uninitialized tags to get

 *   written out to memory, which does really unpleasant things to the main

 *   processor.  We fix this by performing an invalidate, rather than a

 *   clean + invalidate, before jumping into the kernel.

 */

ENTRY(v7_invalidate_l1)

        mov     r0, #0

        mcr     p15, 2, r0, c0, c0, 0

        mrc     p15, 1, r0, c0, c0, 0



        ldr     r1, =0x7fff

        and     r2, r1, r0, lsr #13



        ldr     r1, =0x3ff



        and     r3, r1, r0, lsr #3  @ NumWays - 1

        add     r2, r2, #1          @ NumSets



        and     r0, r0, #0x7

        add     r0, r0, #4          @ SetShift



        clz     r1, r3              @ WayShift

        add     r4, r3, #1          @ NumWays

1:      sub     r2, r2, #1          @ NumSets--

        mov     r3, r4              @ Temp = NumWays

2:      subs    r3, r3, #1          @ Temp--

        mov     r5, r3, lsl r1

        mov     r6, r2, lsl r0

        orr     r5, r5, r6          @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)

        mcr     p15, 0, r5, c7, c6, 2

        bgt     2b

        cmp     r2, #0

        bgt     1b

        dsb

        isb

        mov     pc, lr

ENDPROC(v7_invalidate_l1)







ENTRY(tegra_secondary_startup)

ENTRY(tegra_secondary_startup)

        bl      v7_invalidate_l1

        bl      v7_invalidate_l1

arch/arm/mm/cache-v7.S

+46 −0
Original line number Original line Diff line number Diff line
@@ -18,6 +18,52 @@ 




#include "proc-macros.S"

#include "proc-macros.S"





/*

 * The secondary kernel init calls v7_flush_dcache_all before it enables

 * the L1; however, the L1 comes out of reset in an undefined state, so

 * the clean + invalidate performed by v7_flush_dcache_all causes a bunch

 * of cache lines with uninitialized data and uninitialized tags to get

 * written out to memory, which does really unpleasant things to the main

 * processor.  We fix this by performing an invalidate, rather than a

 * clean + invalidate, before jumping into the kernel.

 *

 * This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs

 * to be called for both secondary cores startup and primary core resume

 * procedures.

 */

ENTRY(v7_invalidate_l1)

       mov     r0, #0

       mcr     p15, 2, r0, c0, c0, 0

       mrc     p15, 1, r0, c0, c0, 0



       ldr     r1, =0x7fff

       and     r2, r1, r0, lsr #13



       ldr     r1, =0x3ff



       and     r3, r1, r0, lsr #3      @ NumWays - 1

       add     r2, r2, #1              @ NumSets



       and     r0, r0, #0x7

       add     r0, r0, #4      @ SetShift



       clz     r1, r3          @ WayShift

       add     r4, r3, #1      @ NumWays

1:     sub     r2, r2, #1      @ NumSets--

       mov     r3, r4          @ Temp = NumWays

2:     subs    r3, r3, #1      @ Temp--

       mov     r5, r3, lsl r1

       mov     r6, r2, lsl r0

       orr     r5, r5, r6      @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)

       mcr     p15, 0, r5, c7, c6, 2

       bgt     2b

       cmp     r2, #0

       bgt     1b

       dsb

       isb

       mov     pc, lr

ENDPROC(v7_invalidate_l1)



/*

/*

 *	v7_flush_icache_all()

 *	v7_flush_icache_all()

 *

 *