Loading arch/arm/kernel/process.c +11 −4 Original line number Diff line number Diff line Loading @@ -168,12 +168,11 @@ void machine_restart(char * __unused) EXPORT_SYMBOL(machine_restart); void show_regs(struct pt_regs * regs) void __show_regs(struct pt_regs *regs) { unsigned long flags; flags = condition_codes(regs); unsigned long flags = condition_codes(regs); printk("CPU: %d\n", smp_processor_id()); print_symbol("PC is at %s\n", instruction_pointer(regs)); print_symbol("LR is at %s\n", regs->ARM_lr); printk("pc : [<%08lx>] lr : [<%08lx>] %s\n" Loading Loading @@ -213,6 +212,14 @@ void show_regs(struct pt_regs * regs) } } void show_regs(struct pt_regs * regs) { printk("\n"); printk("Pid: %d, comm: %20s\n", current->pid, current->comm); __show_regs(regs); __backtrace(); } void show_fpregs(struct user_fp *regs) { int i; Loading arch/arm/kernel/traps.c +2 −6 Original line number Diff line number Diff line Loading @@ -31,9 +31,6 @@ #include "ptrace.h" extern void c_backtrace (unsigned long fp, int pmode); extern void show_pte(struct mm_struct *mm, unsigned long addr); const char *processor_modes[]= { "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" , "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26", Loading Loading @@ -216,8 +213,7 @@ NORET_TYPE void die(const char *str, struct pt_regs *regs, int err) printk("Internal error: %s: %x [#%d]\n", str, err, ++die_counter); print_modules(); printk("CPU: %d\n", smp_processor_id()); show_regs(regs); __show_regs(regs); printk("Process %s (pid: %d, stack limit = 0x%p)\n", tsk->comm, tsk->pid, tsk->thread_info + 1); Loading Loading @@ -482,7 +478,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs) current->pid, current->comm, no); dump_instr(regs); if (user_mode(regs)) { show_regs(regs); __show_regs(regs); c_backtrace(regs->ARM_fp, processor_mode(regs)); } } Loading arch/arm/lib/bitops.h 0 → 100644 +33 −0 Original line number Diff line number Diff line .macro bitop, instr and r2, r0, #7 mov r3, #1 mov r3, r3, lsl r2 save_and_disable_irqs ip, r2 ldrb r2, [r1, r0, lsr #3] \instr r2, r2, r3 strb r2, [r1, r0, lsr #3] restore_irqs ip mov pc, lr .endm /** * testop - implement a test_and_xxx_bit operation. * @instr: operational instruction * @store: store instruction * * Note: we can trivially conditionalise the store instruction * to avoid dirting the data cache. */ .macro testop, instr, store add r1, r1, r0, lsr #3 and r3, r0, #7 mov r0, #1 save_and_disable_irqs ip, r2 ldrb r2, [r1] tst r2, r0, lsl r3 \instr r2, r2, r0, lsl r3 \store r2, [r1] restore_irqs ip moveq r0, #0 mov pc, lr .endm arch/arm/lib/changebit.S +2 −9 Original line number Diff line number Diff line Loading @@ -9,6 +9,7 @@ */ #include <linux/linkage.h> #include <asm/assembler.h> #include "bitops.h" .text /* Purpose : Function to change a bit Loading @@ -17,12 +18,4 @@ ENTRY(_change_bit_be) eor r0, r0, #0x18 @ big endian byte ordering ENTRY(_change_bit_le) and r2, r0, #7 mov r3, #1 mov r3, r3, lsl r2 save_and_disable_irqs ip, r2 ldrb r2, [r1, r0, lsr #3] eor r2, r2, r3 strb r2, [r1, r0, lsr #3] restore_irqs ip RETINSTR(mov,pc,lr) bitop eor arch/arm/lib/clearbit.S +2 −11 Original line number Diff line number Diff line Loading @@ -9,6 +9,7 @@ */ #include <linux/linkage.h> #include <asm/assembler.h> #include "bitops.h" .text /* Loading @@ -18,14 +19,4 @@ ENTRY(_clear_bit_be) eor r0, r0, #0x18 @ big endian byte ordering ENTRY(_clear_bit_le) and r2, r0, #7 mov r3, #1 mov r3, r3, lsl r2 save_and_disable_irqs ip, r2 ldrb r2, [r1, r0, lsr #3] bic r2, r2, r3 strb r2, [r1, r0, lsr #3] restore_irqs ip RETINSTR(mov,pc,lr) bitop bic Loading
arch/arm/kernel/process.c +11 −4 Original line number Diff line number Diff line Loading @@ -168,12 +168,11 @@ void machine_restart(char * __unused) EXPORT_SYMBOL(machine_restart); void show_regs(struct pt_regs * regs) void __show_regs(struct pt_regs *regs) { unsigned long flags; flags = condition_codes(regs); unsigned long flags = condition_codes(regs); printk("CPU: %d\n", smp_processor_id()); print_symbol("PC is at %s\n", instruction_pointer(regs)); print_symbol("LR is at %s\n", regs->ARM_lr); printk("pc : [<%08lx>] lr : [<%08lx>] %s\n" Loading Loading @@ -213,6 +212,14 @@ void show_regs(struct pt_regs * regs) } } void show_regs(struct pt_regs * regs) { printk("\n"); printk("Pid: %d, comm: %20s\n", current->pid, current->comm); __show_regs(regs); __backtrace(); } void show_fpregs(struct user_fp *regs) { int i; Loading
arch/arm/kernel/traps.c +2 −6 Original line number Diff line number Diff line Loading @@ -31,9 +31,6 @@ #include "ptrace.h" extern void c_backtrace (unsigned long fp, int pmode); extern void show_pte(struct mm_struct *mm, unsigned long addr); const char *processor_modes[]= { "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" , "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26", Loading Loading @@ -216,8 +213,7 @@ NORET_TYPE void die(const char *str, struct pt_regs *regs, int err) printk("Internal error: %s: %x [#%d]\n", str, err, ++die_counter); print_modules(); printk("CPU: %d\n", smp_processor_id()); show_regs(regs); __show_regs(regs); printk("Process %s (pid: %d, stack limit = 0x%p)\n", tsk->comm, tsk->pid, tsk->thread_info + 1); Loading Loading @@ -482,7 +478,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs) current->pid, current->comm, no); dump_instr(regs); if (user_mode(regs)) { show_regs(regs); __show_regs(regs); c_backtrace(regs->ARM_fp, processor_mode(regs)); } } Loading
arch/arm/lib/bitops.h 0 → 100644 +33 −0 Original line number Diff line number Diff line .macro bitop, instr and r2, r0, #7 mov r3, #1 mov r3, r3, lsl r2 save_and_disable_irqs ip, r2 ldrb r2, [r1, r0, lsr #3] \instr r2, r2, r3 strb r2, [r1, r0, lsr #3] restore_irqs ip mov pc, lr .endm /** * testop - implement a test_and_xxx_bit operation. * @instr: operational instruction * @store: store instruction * * Note: we can trivially conditionalise the store instruction * to avoid dirting the data cache. */ .macro testop, instr, store add r1, r1, r0, lsr #3 and r3, r0, #7 mov r0, #1 save_and_disable_irqs ip, r2 ldrb r2, [r1] tst r2, r0, lsl r3 \instr r2, r2, r0, lsl r3 \store r2, [r1] restore_irqs ip moveq r0, #0 mov pc, lr .endm
arch/arm/lib/changebit.S +2 −9 Original line number Diff line number Diff line Loading @@ -9,6 +9,7 @@ */ #include <linux/linkage.h> #include <asm/assembler.h> #include "bitops.h" .text /* Purpose : Function to change a bit Loading @@ -17,12 +18,4 @@ ENTRY(_change_bit_be) eor r0, r0, #0x18 @ big endian byte ordering ENTRY(_change_bit_le) and r2, r0, #7 mov r3, #1 mov r3, r3, lsl r2 save_and_disable_irqs ip, r2 ldrb r2, [r1, r0, lsr #3] eor r2, r2, r3 strb r2, [r1, r0, lsr #3] restore_irqs ip RETINSTR(mov,pc,lr) bitop eor
arch/arm/lib/clearbit.S +2 −11 Original line number Diff line number Diff line Loading @@ -9,6 +9,7 @@ */ #include <linux/linkage.h> #include <asm/assembler.h> #include "bitops.h" .text /* Loading @@ -18,14 +19,4 @@ ENTRY(_clear_bit_be) eor r0, r0, #0x18 @ big endian byte ordering ENTRY(_clear_bit_le) and r2, r0, #7 mov r3, #1 mov r3, r3, lsl r2 save_and_disable_irqs ip, r2 ldrb r2, [r1, r0, lsr #3] bic r2, r2, r3 strb r2, [r1, r0, lsr #3] restore_irqs ip RETINSTR(mov,pc,lr) bitop bic