Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6 (c03296a8) · Commits · e / devices / android_kernel_fairphone_FP4

arch/ia64/Kconfig

+3 −1

Original line number	Diff line number	Diff line
		@@ -194,7 +194,6 @@ config IA64_L1_CACHE_SHIFT
		default "7" if MCKINLEY
		default "6" if ITANIUM

		# align cache-sensitive data to 64 bytes
		config IA64_CYCLONE
		bool "Cyclone (EXA) Time Source support"
		help
		@@ -374,6 +373,9 @@ config IA64_PALINFO
		To use this option, you have to ensure that the "/proc file system
		support" (CONFIG_PROC_FS) is enabled, too.

		config SGI_SN
		def_bool y if (IA64_SGI_SN2 \|\| IA64_GENERIC)

		source "drivers/firmware/Kconfig"

		source "fs/Kconfig.binfmt"

arch/ia64/kernel/sal.c

+75 −0

Original line number	Diff line number	Diff line
		@@ -14,6 +14,7 @@
		#include <linux/spinlock.h>
		#include <linux/string.h>

		#include <asm/delay.h>
		#include <asm/page.h>
		#include <asm/sal.h>
		#include <asm/pal.h>
		@@ -214,6 +215,78 @@ chk_nointroute_opt(void)
		static void __init sal_desc_ap_wakeup(void *p) { }
		#endif

		/*
		* HP rx5670 firmware polls for interrupts during SAL_CACHE_FLUSH by reading
		* cr.ivr, but it never writes cr.eoi. This leaves any interrupt marked as
		* "in-service" and masks other interrupts of equal or lower priority.
		*
		* HP internal defect reports: F1859, F2775, F3031.
		*/
		static int sal_cache_flush_drops_interrupts;

		static void __init
		check_sal_cache_flush (void)
		{
		unsigned long flags, itv;
		int cpu;
		u64 vector;

		cpu = get_cpu();
		local_irq_save(flags);

		/*
		* Schedule a timer interrupt, wait until it's reported, and see if
		* SAL_CACHE_FLUSH drops it.
		*/
		itv = ia64_get_itv();
		BUG_ON((itv & (1 << 16)) == 0);

		ia64_set_itv(IA64_TIMER_VECTOR);
		ia64_set_itm(ia64_get_itc() + 1000);

		while (!ia64_get_irr(IA64_TIMER_VECTOR))
		cpu_relax();

		ia64_sal_cache_flush(3);

		if (ia64_get_irr(IA64_TIMER_VECTOR)) {
		vector = ia64_get_ivr();
		ia64_eoi();
		WARN_ON(vector != IA64_TIMER_VECTOR);
		} else {
		sal_cache_flush_drops_interrupts = 1;
		printk(KERN_ERR "SAL: SAL_CACHE_FLUSH drops interrupts; "
		"PAL_CACHE_FLUSH will be used instead\n");
		ia64_eoi();
		}

		ia64_set_itv(itv);
		local_irq_restore(flags);
		put_cpu();
		}

		s64
		ia64_sal_cache_flush (u64 cache_type)
		{
		struct ia64_sal_retval isrv;

		if (sal_cache_flush_drops_interrupts) {
		unsigned long flags;
		u64 progress;
		s64 rc;

		progress = 0;
		local_irq_save(flags);
		rc = ia64_pal_cache_flush(cache_type,
		PAL_CACHE_FLUSH_INVALIDATE, &progress, NULL);
		local_irq_restore(flags);
		return rc;
		}

		SAL_CALL(isrv, SAL_CACHE_FLUSH, cache_type, 0, 0, 0, 0, 0, 0);
		return isrv.status;
		}

		void __init
		ia64_sal_init (struct ia64_sal_systab *systab)
		{
		@@ -262,6 +335,8 @@ ia64_sal_init (struct ia64_sal_systab *systab)
		}
		p += SAL_DESC_SIZE(*p);
		}

		check_sal_cache_flush();
		}

		int

arch/ia64/sn/Makefile

+0 −2

Original line number	Diff line number	Diff line
		@@ -9,6 +9,4 @@
		# Makefile for the sn ia64 subplatform
		#

		CPPFLAGS += -I$(srctree)/arch/ia64/sn/include

		obj-y += kernel/ pci/

arch/ia64/sn/kernel/Makefile

+2 −0

Original line number	Diff line number	Diff line
		@@ -7,6 +7,8 @@
		# Copyright (C) 1999,2001-2005 Silicon Graphics, Inc. All Rights Reserved.
		#

		CPPFLAGS += -I$(srctree)/arch/ia64/sn/include

		obj-y += setup.o bte.o bte_error.o irq.o mca.o idle.o \
		huberror.o io_init.o iomv.o klconflib.o sn2/
		obj-$(CONFIG_IA64_GENERIC) += machvec.o

arch/ia64/sn/kernel/bte.c

+6 −11

Original line number	Diff line number	Diff line
		@@ -3,7 +3,7 @@
		* License. See the file "COPYING" in the main directory of this archive
		* for more details.
		*
		* Copyright (c) 2000-2005 Silicon Graphics, Inc. All Rights Reserved.
		* Copyright (c) 2000-2006 Silicon Graphics, Inc. All Rights Reserved.
		*/

		#include <linux/config.h>
		@@ -186,18 +186,13 @@ bte_result_t bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification)

		/* Initialize the notification to a known value. */
		*bte->most_rcnt_na = BTE_WORD_BUSY;
		notif_phys_addr = TO_PHYS(ia64_tpa((unsigned long)bte->most_rcnt_na));
		notif_phys_addr = (u64)bte->most_rcnt_na;

		if (is_shub2()) {
		src = SH2_TIO_PHYS_TO_DMA(src);
		dest = SH2_TIO_PHYS_TO_DMA(dest);
		notif_phys_addr = SH2_TIO_PHYS_TO_DMA(notif_phys_addr);
		}
		/* Set the source and destination registers */
		BTE_PRINTKV(("IBSA = 0x%lx)\n", (TO_PHYS(src))));
		BTE_SRC_STORE(bte, TO_PHYS(src));
		BTE_PRINTKV(("IBDA = 0x%lx)\n", (TO_PHYS(dest))));
		BTE_DEST_STORE(bte, TO_PHYS(dest));
		BTE_PRINTKV(("IBSA = 0x%lx)\n", src));
		BTE_SRC_STORE(bte, src);
		BTE_PRINTKV(("IBDA = 0x%lx)\n", dest));
		BTE_DEST_STORE(bte, dest);

		/* Set the notification register */
		BTE_PRINTKV(("IBNA = 0x%lx)\n", notif_phys_addr));