Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c0034c30 authored by Janne Huttunen's avatar Janne Huttunen Committed by Ralf Baechle
Browse files

MIPS: Octeon: Fix CN6880 hang on XAUI init 



Some CN68XX series Octeon II chips seem to hang if a reset is issued on
XAUI initialization. Avoid the hang by disabling the reset on affected
models. Tested on Cavium EBB6800 evaluation board and Kontron S1901 board.

Signed-off-by: default avatarJanne Huttunen <janne.huttunen@nokia.com>
Signed-off-by: default avatarAaro Koskinen <aaro.koskinen@nokia.com>
Acked-by: default avatarDavid Daney <david.daney@cavium.com>
Cc: David Daney <ddaney.cavm@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Janne Huttunen <janne.huttunen@nokia.com>
Cc: Aaro Koskinen <aaro.koskinen@nokia.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: devel@driverdev.osuosl.org
Patchwork: http://patchwork.linux-mips.org/patch/10970/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent af0cfb2c

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c

+6 −1
Original line number Diff line number Diff line
@@ -151,7 +151,12 @@ int __cvmx_helper_xaui_enable(int interface) 
	/* (4)c Aply reset sequence */

	xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));

	xauiCtl.s.lo_pwr = 0;



	/* Issuing a reset here seems to hang some CN68XX chips. */

	if (!OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X) &&

	    !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X))

		xauiCtl.s.reset = 1;



	cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);



	/* Wait for PCS to come out of reset */