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Commit bfd5e378 authored by Yong Zhao's avatar Yong Zhao Committed by Oded Gabbay
Browse files

drm/amdkfd: Cleanup DQM ASIC-specific ops 



Remove empty initialize function.

Rename register_process to update_qpd to avoid confusion with the
non-ASIC-specific register_process.

Shorten ops_asic_specific to asic_ops.

Signed-off-by: default avatarYong Zhao <yong.zhao@amd.com>
Signed-off-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: default avatarOded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: default avatarOded Gabbay <oded.gabbay@gmail.com>
parent 5a29ad6b

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c

+7 −12
Original line number Diff line number Diff line
@@ -467,7 +467,7 @@ static int register_process(struct device_queue_manager *dqm, 
	mutex_lock(&dqm->lock);

	list_add(&n->list, &dqm->queues);



	retval = dqm->ops_asic_specific.register_process(dqm, qpd);

	retval = dqm->asic_ops.update_qpd(dqm, qpd);



	dqm->processes_count++;
@@ -629,7 +629,7 @@ static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm, 
	pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id);

	pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id);



	dqm->ops_asic_specific.init_sdma_vm(dqm, q, qpd);

	dqm->asic_ops.init_sdma_vm(dqm, q, qpd);

	retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,

				&q->gart_mqd_addr, &q->properties);

	if (retval)
@@ -696,8 +696,6 @@ static int set_sched_resources(struct device_queue_manager *dqm) 


static int initialize_cpsch(struct device_queue_manager *dqm)

{

	int retval;



	pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));



	mutex_init(&dqm->lock);
@@ -706,11 +704,8 @@ static int initialize_cpsch(struct device_queue_manager *dqm) 
	dqm->sdma_queue_count = 0;

	dqm->active_runlist = false;

	dqm->sdma_bitmap = (1 << CIK_SDMA_QUEUES) - 1;

	retval = dqm->ops_asic_specific.initialize(dqm);

	if (retval)

		mutex_destroy(&dqm->lock);



	return retval;

	return 0;

}



static int start_cpsch(struct device_queue_manager *dqm)
@@ -850,7 +845,7 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, 
		goto out;

	}



	dqm->ops_asic_specific.init_sdma_vm(dqm, q, qpd);

	dqm->asic_ops.init_sdma_vm(dqm, q, qpd);

	retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,

				&q->gart_mqd_addr, &q->properties);

	if (retval)
@@ -1095,7 +1090,7 @@ static bool set_cache_memory_policy(struct device_queue_manager *dqm, 
		qpd->sh_mem_ape1_limit = limit >> 16;

	}



	retval = dqm->ops_asic_specific.set_cache_memory_policy(

	retval = dqm->asic_ops.set_cache_memory_policy(

			dqm,

			qpd,

			default_policy,
@@ -1270,11 +1265,11 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) 


	switch (dev->device_info->asic_family) {

	case CHIP_CARRIZO:

		device_queue_manager_init_vi(&dqm->ops_asic_specific);

		device_queue_manager_init_vi(&dqm->asic_ops);

		break;



	case CHIP_KAVERI:

		device_queue_manager_init_cik(&dqm->ops_asic_specific);

		device_queue_manager_init_cik(&dqm->asic_ops);

		break;

	default:

		WARN(1, "Unexpected ASIC family %u",

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h

+6 −5
Original line number Diff line number Diff line
@@ -128,9 +128,8 @@ struct device_queue_manager_ops { 
};



struct device_queue_manager_asic_ops {

	int	(*register_process)(struct device_queue_manager *dqm,

	int	(*update_qpd)(struct device_queue_manager *dqm,

					struct qcm_process_device *qpd);

	int	(*initialize)(struct device_queue_manager *dqm);

	bool	(*set_cache_memory_policy)(struct device_queue_manager *dqm,

					   struct qcm_process_device *qpd,

					   enum cache_policy default_policy,
@@ -156,7 +155,7 @@ struct device_queue_manager_asic_ops { 


struct device_queue_manager {

	struct device_queue_manager_ops ops;

	struct device_queue_manager_asic_ops ops_asic_specific;

	struct device_queue_manager_asic_ops asic_ops;



	struct mqd_manager	*mqds[KFD_MQD_TYPE_MAX];

	struct packet_manager	packets;
@@ -179,8 +178,10 @@ struct device_queue_manager { 
	bool			active_runlist;

};



void device_queue_manager_init_cik(struct device_queue_manager_asic_ops *ops);

void device_queue_manager_init_vi(struct device_queue_manager_asic_ops *ops);

void device_queue_manager_init_cik(

		struct device_queue_manager_asic_ops *asic_ops);

void device_queue_manager_init_vi(

		struct device_queue_manager_asic_ops *asic_ops);

void program_sh_mem_settings(struct device_queue_manager *dqm,

					struct qcm_process_device *qpd);

unsigned int get_queues_num(struct device_queue_manager *dqm);

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c

+7 −13
Original line number Diff line number Diff line
@@ -32,18 +32,17 @@ static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm, 
				   enum cache_policy alternate_policy,

				   void __user *alternate_aperture_base,

				   uint64_t alternate_aperture_size);

static int register_process_cik(struct device_queue_manager *dqm,

static int update_qpd_cik(struct device_queue_manager *dqm,

					struct qcm_process_device *qpd);

static int initialize_cpsch_cik(struct device_queue_manager *dqm);

static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,

				struct qcm_process_device *qpd);



void device_queue_manager_init_cik(struct device_queue_manager_asic_ops *ops)

void device_queue_manager_init_cik(

		struct device_queue_manager_asic_ops *asic_ops)

{

	ops->set_cache_memory_policy = set_cache_memory_policy_cik;

	ops->register_process = register_process_cik;

	ops->initialize = initialize_cpsch_cik;

	ops->init_sdma_vm = init_sdma_vm;

	asic_ops->set_cache_memory_policy = set_cache_memory_policy_cik;

	asic_ops->update_qpd = update_qpd_cik;

	asic_ops->init_sdma_vm = init_sdma_vm;

}



static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble)
@@ -99,7 +98,7 @@ static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm, 
	return true;

}



static int register_process_cik(struct device_queue_manager *dqm,

static int update_qpd_cik(struct device_queue_manager *dqm,

		struct qcm_process_device *qpd)

{

	struct kfd_process_device *pdd;
@@ -148,8 +147,3 @@ static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q, 


	q->properties.sdma_vm_addr = value;

}
 


static int initialize_cpsch_cik(struct device_queue_manager *dqm)

{

	return 0;

}

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c

+7 −13
Original line number Diff line number Diff line
@@ -33,18 +33,17 @@ static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm, 
				   enum cache_policy alternate_policy,

				   void __user *alternate_aperture_base,

				   uint64_t alternate_aperture_size);

static int register_process_vi(struct device_queue_manager *dqm,

static int update_qpd_vi(struct device_queue_manager *dqm,

					struct qcm_process_device *qpd);

static int initialize_cpsch_vi(struct device_queue_manager *dqm);

static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,

				struct qcm_process_device *qpd);



void device_queue_manager_init_vi(struct device_queue_manager_asic_ops *ops)

void device_queue_manager_init_vi(

		struct device_queue_manager_asic_ops *asic_ops)

{

	ops->set_cache_memory_policy = set_cache_memory_policy_vi;

	ops->register_process = register_process_vi;

	ops->initialize = initialize_cpsch_vi;

	ops->init_sdma_vm = init_sdma_vm;

	asic_ops->set_cache_memory_policy = set_cache_memory_policy_vi;

	asic_ops->update_qpd = update_qpd_vi;

	asic_ops->init_sdma_vm = init_sdma_vm;

}



static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble)
@@ -104,7 +103,7 @@ static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm, 
	return true;

}



static int register_process_vi(struct device_queue_manager *dqm,

static int update_qpd_vi(struct device_queue_manager *dqm,

					struct qcm_process_device *qpd)

{

	struct kfd_process_device *pdd;
@@ -160,8 +159,3 @@ static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q, 


	q->properties.sdma_vm_addr = value;

}
 


static int initialize_cpsch_vi(struct device_queue_manager *dqm)

{

	return 0;

}