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Commit bf02f2ff authored by Madalin Bucur's avatar Madalin Bucur Committed by Shawn Guo
Browse files

arm64: dts: add LS1043A DPAA FMan support



Add the DPAA 1.x FMan device tree nodes for LS1043A boards.

Signed-off-by: default avatarMadalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 1ffbecdd
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+45 −0
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/*
 * QorIQ FMan v3 device tree nodes for ls1043
 *
 * Copyright 2015-2016 Freescale Semiconductor Inc.
 *
 * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
 */

&soc {

/* include used FMan blocks */
#include "qoriq-fman3-0.dtsi"
#include "qoriq-fman3-0-1g-0.dtsi"
#include "qoriq-fman3-0-1g-1.dtsi"
#include "qoriq-fman3-0-1g-2.dtsi"
#include "qoriq-fman3-0-1g-3.dtsi"
#include "qoriq-fman3-0-1g-4.dtsi"
#include "qoriq-fman3-0-1g-5.dtsi"
#include "qoriq-fman3-0-10g-0.dtsi"

};

&fman0 {
	/* these aliases provide the FMan ports mapping */
	enet0: ethernet@e0000 {
	};

	enet1: ethernet@e2000 {
	};

	enet2: ethernet@e4000 {
	};

	enet3: ethernet@e6000 {
	};

	enet4: ethernet@e8000 {
	};

	enet5: ethernet@ea000 {
	};

	enet6: ethernet@f0000 {
	};
};
+2 −0
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@@ -181,3 +181,5 @@
		reg = <0>;
	};
};

#include "fsl-ls1043-post.dtsi"
+73 −0
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@@ -139,3 +139,76 @@
&duart1 {
	status = "okay";
};

#include "fsl-ls1043-post.dtsi"

&fman0 {
	ethernet@e0000 {
		phy-handle = <&qsgmii_phy1>;
		phy-connection-type = "qsgmii";
	};

	ethernet@e2000 {
		phy-handle = <&qsgmii_phy2>;
		phy-connection-type = "qsgmii";
	};

	ethernet@e4000 {
		phy-handle = <&rgmii_phy1>;
		phy-connection-type = "rgmii-txid";
	};

	ethernet@e6000 {
		phy-handle = <&rgmii_phy2>;
		phy-connection-type = "rgmii-txid";
	};

	ethernet@e8000 {
		phy-handle = <&qsgmii_phy3>;
		phy-connection-type = "qsgmii";
	};

	ethernet@ea000 {
		phy-handle = <&qsgmii_phy4>;
		phy-connection-type = "qsgmii";
	};

	ethernet@f0000 { /* 10GEC1 */
		phy-handle = <&aqr105_phy>;
		phy-connection-type = "xgmii";
	};

	mdio@fc000 {
		rgmii_phy1: ethernet-phy@1 {
			reg = <0x1>;
		};

		rgmii_phy2: ethernet-phy@2 {
			reg = <0x2>;
		};

		qsgmii_phy1: ethernet-phy@4 {
			reg = <0x4>;
		};

		qsgmii_phy2: ethernet-phy@5 {
			reg = <0x5>;
		};

		qsgmii_phy3: ethernet-phy@6 {
			reg = <0x6>;
		};

		qsgmii_phy4: ethernet-phy@7 {
			reg = <0x7>;
		};
	};

	mdio@fd000 {
		aqr105_phy: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c45";
			interrupts = <0 132 4>;
			reg = <0x1>;
		};
	};
};
+12 −1
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@@ -53,6 +53,17 @@
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		fman0 = &fman0;
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		ethernet3 = &enet3;
		ethernet4 = &enet4;
		ethernet5 = &enet5;
		ethernet6 = &enet6;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
@@ -180,7 +191,7 @@
		interrupts = <1 9 0xf08>;
	};

	soc {
	soc: soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;