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Commit befb63b4 authored by oulijun's avatar oulijun Committed by Doug Ledford
Browse files

RDMA/hns: Set sq_cur_sge_blk_addr field in QPC in hip08 



If the extend sges exist, the sq_cur_sge_blk_addr field in QPC
(qp context) should be configured.

Signed-off-by: default avatarLijun Ou <oulijun@huawei.com>
Signed-off-by: default avatarShaobo Xu <xushaobo2@huawei.com>
Signed-off-by: default avatarWei Hu (Xavier) <xavier.huwei@huawei.com>
Signed-off-by: default avatarYixian Liu <liuyixian@huawei.com>
Signed-off-by: default avatarDoug Ledford <dledford@redhat.com>
parent a49d761f

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+16 −0
Original line number Diff line number Diff line
@@ -2566,6 +2566,7 @@ static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 
	struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);

	struct device *dev = hr_dev->dev;

	dma_addr_t dma_handle;

	u32 page_size;

	u64 *mtts;



	/* Search qp buf's mtts */
@@ -2608,6 +2609,21 @@ static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 
		       V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,

		       V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0);



	page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);

	context->sq_cur_sge_blk_addr = hr_qp->sq.max_gs > 2 ?

				      ((u32)(mtts[hr_qp->sge.offset / page_size]

				      >> PAGE_ADDR_SHIFT)) : 0;

	roce_set_field(context->byte_184_irrl_idx,

		       V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,

		       V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S,

		       hr_qp->sq.max_gs > 2 ?

		       (mtts[hr_qp->sge.offset / page_size] >>

		       (32 + PAGE_ADDR_SHIFT)) : 0);

	qpc_mask->sq_cur_sge_blk_addr = 0;

	roce_set_field(qpc_mask->byte_184_irrl_idx,

		       V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,

		       V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0);



	context->rx_sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);

	roce_set_field(context->byte_232_irrl_sge,

		       V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

+1 −1
Original line number Diff line number Diff line
@@ -353,7 +353,7 @@ struct hns_roce_v2_qp_context { 
	u32	byte_168_irrl_idx;

	u32	byte_172_sq_psn;

	u32	byte_176_msg_pktn;

	u32	sq_cur_sqe_blk_addr;

	u32	sq_cur_sge_blk_addr;

	u32	byte_184_irrl_idx;

	u32	cur_sge_offset;

	u32	byte_192_ext_sge;