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Commit bef94596 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'depends/clk/clk-next' into next/clock 



Mike Turquette <mturquette@ti.com> has asked me to take the clock
changes through the arm-soc tree while there are still so many
inderdependencies, so this is the entire branch.

* depends/clk/clk-next: (30 commits)
  clk: add a fixed factor clock
  clk: mux: assign init data
  clk: remove COMMON_CLK_DISABLE_UNUSED
  clk: prevent spurious parent rate propagation
  MAINTAINERS: add entry for common clk framework
  clk: clk_set_rate() must fail if CLK_SET_RATE_GATE is set and clk is enabled
  clk: Use a separate struct for holding init data.
  clk: constify parent name arrays in macros
  clk: remove trailing whitespace from clk.h
  clk: select CLKDEV_LOOKUP for COMMON_CLK
  clk: Don't set clk->new_rate twice
  clk: clk-private: Add DEFINE_CLK macro
  clk: clk-gate: Create clk_gate_endisable()
  clk: Fix typo in comment
  clk: propagate round_rate for CLK_SET_RATE_PARENT case
  clk: pass parent_rate into .set_rate
  clk: always pass parent_rate into .round_rate
  clk: basic: improve parent_names & return errors
  clk: core: copy parent_names & return error codes
  clk: Constify parent name arrays
  ...

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 66f75a5d f0948f59

MAINTAINERS

+10 −0
Original line number Original line Diff line number Diff line
@@ -1882,6 +1882,16 @@ F: Documentation/filesystems/coda.txt 
F:	fs/coda/

F:	fs/coda/

F:	include/linux/coda*.h

F:	include/linux/coda*.h





COMMON CLK FRAMEWORK

M:	Mike Turquette <mturquette@ti.com>

M:	Mike Turquette <mturquette@linaro.org>

L:	linux-arm-kernel@lists.infradead.org (same as CLK API & CLKDEV)

T:	git git://git.linaro.org/people/mturquette/linux.git

S:	Maintained

F:	drivers/clk/clk.c

F:	drivers/clk/clk-*

F:	include/linux/clk-pr*



COMMON INTERNET FILE SYSTEM (CIFS)

COMMON INTERNET FILE SYSTEM (CIFS)

M:	Steve French <sfrench@samba.org>

M:	Steve French <sfrench@samba.org>

L:	linux-cifs@vger.kernel.org

L:	linux-cifs@vger.kernel.org

drivers/clk/Kconfig

+1 −11
Original line number Original line Diff line number Diff line
@@ -12,6 +12,7 @@ config HAVE_MACH_CLKDEV 
config COMMON_CLK

config COMMON_CLK

	bool

	bool

	select HAVE_CLK_PREPARE

	select HAVE_CLK_PREPARE

	select CLKDEV_LOOKUP

	---help---

	---help---

	  The common clock framework is a single definition of struct

	  The common clock framework is a single definition of struct

	  clk, useful across many platforms, as well as an

	  clk, useful across many platforms, as well as an
@@ -22,17 +23,6 @@ config COMMON_CLK 
menu "Common Clock Framework"

menu "Common Clock Framework"

	depends on COMMON_CLK

	depends on COMMON_CLK





config COMMON_CLK_DISABLE_UNUSED

	bool "Disabled unused clocks at boot"

	depends on COMMON_CLK

	---help---

	  Traverses the entire clock tree and disables any clocks that are

	  enabled in hardware but have not been enabled by any device drivers.

	  This saves power and keeps the software model of the clock in line

	  with reality.



	  If in doubt, say "N".



config COMMON_CLK_DEBUG

config COMMON_CLK_DEBUG

	bool "DebugFS representation of clock tree"

	bool "DebugFS representation of clock tree"

	depends on COMMON_CLK

	depends on COMMON_CLK

drivers/clk/Makefile

+1 −1
Original line number Original line Diff line number Diff line 




obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o

obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o

obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed-rate.o clk-gate.o \

obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed-rate.o clk-gate.o \

				   clk-mux.o clk-divider.o
 
				   clk-mux.o clk-divider.o clk-fixed-factor.o

drivers/clk/clk-divider.c

+34 −34
Original line number Original line Diff line number Diff line
@@ -45,7 +45,6 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, 




	return parent_rate / div;

	return parent_rate / div;

}

}

EXPORT_SYMBOL_GPL(clk_divider_recalc_rate);





/*

/*

 * The reverse of DIV_ROUND_UP: The maximum number which

 * The reverse of DIV_ROUND_UP: The maximum number which
@@ -68,8 +67,8 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, 
	if (divider->flags & CLK_DIVIDER_ONE_BASED)

	if (divider->flags & CLK_DIVIDER_ONE_BASED)

		maxdiv--;

		maxdiv--;





	if (!best_parent_rate) {

	if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {

		parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));

		parent_rate = *best_parent_rate;

		bestdiv = DIV_ROUND_UP(parent_rate, rate);

		bestdiv = DIV_ROUND_UP(parent_rate, rate);

		bestdiv = bestdiv == 0 ? 1 : bestdiv;

		bestdiv = bestdiv == 0 ? 1 : bestdiv;

		bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;

		bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
@@ -109,24 +108,18 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, 
	int div;

	int div;

	div = clk_divider_bestdiv(hw, rate, prate);

	div = clk_divider_bestdiv(hw, rate, prate);





	if (prate)

	return *prate / div;

	return *prate / div;

	else {

		unsigned long r;

		r = __clk_get_rate(__clk_get_parent(hw->clk));

		return r / div;

}

}

}

EXPORT_SYMBOL_GPL(clk_divider_round_rate);





static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)

static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,

				unsigned long parent_rate)

{

{

	struct clk_divider *divider = to_clk_divider(hw);

	struct clk_divider *divider = to_clk_divider(hw);

	unsigned int div;

	unsigned int div;

	unsigned long flags = 0;

	unsigned long flags = 0;

	u32 val;

	u32 val;





	div = __clk_get_rate(__clk_get_parent(hw->clk)) / rate;

	div = parent_rate / rate;





	if (!(divider->flags & CLK_DIVIDER_ONE_BASED))

	if (!(divider->flags & CLK_DIVIDER_ONE_BASED))

		div--;

		div--;
@@ -147,15 +140,26 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate) 




	return 0;

	return 0;

}

}

EXPORT_SYMBOL_GPL(clk_divider_set_rate);





struct clk_ops clk_divider_ops = {

const struct clk_ops clk_divider_ops = {

	.recalc_rate = clk_divider_recalc_rate,

	.recalc_rate = clk_divider_recalc_rate,

	.round_rate = clk_divider_round_rate,

	.round_rate = clk_divider_round_rate,

	.set_rate = clk_divider_set_rate,

	.set_rate = clk_divider_set_rate,

};

};

EXPORT_SYMBOL_GPL(clk_divider_ops);

EXPORT_SYMBOL_GPL(clk_divider_ops);





/**

 * clk_register_divider - register a divider clock with the clock framework

 * @dev: device registering this clock

 * @name: name of this clock

 * @parent_name: name of clock's parent

 * @flags: framework-specific flags

 * @reg: register address to adjust divider

 * @shift: number of bits to shift the bitfield

 * @width: width of the bitfield

 * @clk_divider_flags: divider-specific flags for this clock

 * @lock: shared register lock for this clock

 */

struct clk *clk_register_divider(struct device *dev, const char *name,

struct clk *clk_register_divider(struct device *dev, const char *name,

		const char *parent_name, unsigned long flags,

		const char *parent_name, unsigned long flags,

		void __iomem *reg, u8 shift, u8 width,

		void __iomem *reg, u8 shift, u8 width,
@@ -163,38 +167,34 @@ struct clk *clk_register_divider(struct device *dev, const char *name, 
{

{

	struct clk_divider *div;

	struct clk_divider *div;

	struct clk *clk;

	struct clk *clk;

	struct clk_init_data init;





	/* allocate the divider */

	div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);

	div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);



	if (!div) {

	if (!div) {

		pr_err("%s: could not allocate divider clk\n", __func__);

		pr_err("%s: could not allocate divider clk\n", __func__);

		return NULL;

		return ERR_PTR(-ENOMEM);

	}

	}





	init.name = name;

	init.ops = &clk_divider_ops;

	init.flags = flags;

	init.parent_names = (parent_name ? &parent_name: NULL);

	init.num_parents = (parent_name ? 1 : 0);



	/* struct clk_divider assignments */

	/* struct clk_divider assignments */

	div->reg = reg;

	div->reg = reg;

	div->shift = shift;

	div->shift = shift;

	div->width = width;

	div->width = width;

	div->flags = clk_divider_flags;

	div->flags = clk_divider_flags;

	div->lock = lock;

	div->lock = lock;

	div->hw.init = &init;





	if (parent_name) {

	/* register the clock */

		div->parent[0] = kstrdup(parent_name, GFP_KERNEL);

	clk = clk_register(dev, &div->hw);

		if (!div->parent[0])

			goto out;

	}



	clk = clk_register(dev, name,

			&clk_divider_ops, &div->hw,

			div->parent,

			(parent_name ? 1 : 0),

			flags);

	if (clk)

		return clk;





out:

	if (IS_ERR(clk))

	kfree(div->parent[0]);

		kfree(div);

		kfree(div);





	return NULL;

	return clk;

}
 
}

drivers/clk/clk-fixed-factor.c

0 → 100644
+95 −0
Original line number Original line Diff line number Diff line 
/*

 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * Standard functionality for the common clock API.

 */

#include <linux/module.h>

#include <linux/clk-provider.h>

#include <linux/slab.h>

#include <linux/err.h>



/*

 * DOC: basic fixed multiplier and divider clock that cannot gate

 *

 * Traits of this clock:

 * prepare - clk_prepare only ensures that parents are prepared

 * enable - clk_enable only ensures that parents are enabled

 * rate - rate is fixed.  clk->rate = parent->rate / div * mult

 * parent - fixed parent.  No clk_set_parent support

 */



#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)



static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,

		unsigned long parent_rate)

{

	struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);



	return parent_rate * fix->mult / fix->div;

}



static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate,

				unsigned long *prate)

{

	struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);



	if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {

		unsigned long best_parent;



		best_parent = (rate / fix->mult) * fix->div;

		*prate = __clk_round_rate(__clk_get_parent(hw->clk),

				best_parent);

	}



	return (*prate / fix->div) * fix->mult;

}



static int clk_factor_set_rate(struct clk_hw *hw, unsigned long rate,

				unsigned long parent_rate)

{

	return 0;

}



struct clk_ops clk_fixed_factor_ops = {

	.round_rate = clk_factor_round_rate,

	.set_rate = clk_factor_set_rate,

	.recalc_rate = clk_factor_recalc_rate,

};

EXPORT_SYMBOL_GPL(clk_fixed_factor_ops);



struct clk *clk_register_fixed_factor(struct device *dev, const char *name,

		const char *parent_name, unsigned long flags,

		unsigned int mult, unsigned int div)

{

	struct clk_fixed_factor *fix;

	struct clk_init_data init;

	struct clk *clk;



	fix = kmalloc(sizeof(*fix), GFP_KERNEL);

	if (!fix) {

		pr_err("%s: could not allocate fixed factor clk\n", __func__);

		return ERR_PTR(-ENOMEM);

	}



	/* struct clk_fixed_factor assignments */

	fix->mult = mult;

	fix->div = div;

	fix->hw.init = &init;



	init.name = name;

	init.ops = &clk_fixed_factor_ops;

	init.flags = flags;

	init.parent_names = &parent_name;

	init.num_parents = 1;



	clk = clk_register(dev, &fix->hw);



	if (IS_ERR(clk))

		kfree(fix);



	return clk;

}