Commit bebbc4bc authored Sep 15, 2016 by Scott Telford Committed by Max Filippov Sep 19, 2016

xtensa: Tweak xuartps UART driver Rx watermark for Cadence CSP config.



Add module parameter xilinx_uartps.rx_trigger_level=32 to command line
options for CSP to set Rx watermark for xuartps driver lower than the
default value, to avoid UART overruns at 115200 bps.

Signed-off-by: Scott Telford <stelford@cadence.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

parent bf15f86b

arch/xtensa/boot/dts/csp.dts

+1 −1

Original line number	Diff line number	Diff line
		@@ -7,7 +7,7 @@
		interrupt-parent = <&pic>;

		chosen {
		bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw earlyprintk loglevel=8 nohz=off ignore_loglevel";
		bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw earlyprintk xilinx_uartps.rx_trigger_level=32 loglevel=8 nohz=off ignore_loglevel";
		};

		memory@0 {