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Commit bdf6bfb3 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branch 'clk-hikey' into clk-next 

* clk-hikey:
  clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu'
  clk: hisilicon: Delete an error message for a failed memory allocation in hisi_register_clkgate_sep()
  clk: hi3660: fix incorrect uart3 clock freqency
  clk: hi6220: mark clock cs_atb_syspll as critical
parents 042e2e9c 3320f39b

drivers/clk/hisilicon/clk-hi3660.c

+1 −1
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = { 


/* crgctrl */

static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = {

	{ HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 8, 0, },

	{ HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 16, 0, },

	{ HI3660_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys", 1, 6, 0, },

	{ HI3660_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_iomcu", 1, 4, 0, },

	{ HI3660_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_iomcu", 1, 4, 0, },

drivers/clk/hisilicon/clk-hi6220.c

+1 −1
Original line number Diff line number Diff line
@@ -145,7 +145,7 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = { 
	{ HI6220_BBPPLL_SEL,    "bbppll_sel",    "pll0_bbp_gate",  CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 9,  0, },

	{ HI6220_MEDIA_PLL_SRC, "media_pll_src", "pll_media_gate", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 10, 0, },

	{ HI6220_MMC2_SEL,      "mmc2_sel",      "mmc2_mux1",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 11, 0, },

	{ HI6220_CS_ATB_SYSPLL, "cs_atb_syspll", "syspll",         CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 12, 0, },

	{ HI6220_CS_ATB_SYSPLL, "cs_atb_syspll", "syspll",         CLK_SET_RATE_PARENT|CLK_IS_CRITICAL,   0x270, 12, 0, },

};



static struct hisi_mux_clock hi6220_mux_clks_sys[] __initdata = {

drivers/clk/hisilicon/clkgate-separated.c

+1 −3
Original line number Diff line number Diff line
@@ -105,10 +105,8 @@ struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name, 
	struct clk_init_data init;



	sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);

	if (!sclk) {

		pr_err("%s: fail to allocate separated gated clk\n", __func__);

	if (!sclk)

		return ERR_PTR(-ENOMEM);

	}



	init.name = name;

	init.ops = &clkgate_separated_ops;

drivers/clk/hisilicon/crg-hi3798cv200.c

+11 −1
Original line number Diff line number Diff line
@@ -47,6 +47,8 @@ 
#define HI3798CV200_FIXED_12M	81

#define HI3798CV200_FIXED_48M	82

#define HI3798CV200_FIXED_60M	83

#define HI3798CV200_FIXED_166P5M	84

#define HI3798CV200_SDIO0_MUX	85



#define HI3798CV200_CRG_NR_CLKS		128
@@ -63,6 +65,7 @@ static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = { 
	{ HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },

	{ HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, },

	{ HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, },

	{ HI3798CV200_FIXED_166P5M, "166p5m", NULL, 0, 165000000, },

	{ HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, },

	{ HI3798CV200_FIXED_250M, "250m", NULL, 0, 250000000, },

};
@@ -75,12 +78,19 @@ static const char *const comphy1_mux_p[] = { 
		"100m", "25m"};

static u32 comphy1_mux_table[] = {2, 3};



static const char *const sdio_mux_p[] = {

		"100m", "50m", "150m", "166p5m" };

static u32 sdio_mux_table[] = {0, 1, 2, 3};



static struct hisi_mux_clock hi3798cv200_mux_clks[] = {

	{ HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),

		CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },

	{ HI3798CV200_COMBPHY1_MUX, "combphy1_mux",

		comphy1_mux_p, ARRAY_SIZE(comphy1_mux_p),

		CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy1_mux_table, },

	{ HI3798CV200_SDIO0_MUX, "sdio0_mux", sdio_mux_p,

		ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT,

		0x9c, 8, 2, 0, sdio_mux_table, },

};



static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
@@ -104,7 +114,7 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = { 
	/* SDIO */

	{ HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m",

			CLK_SET_RATE_PARENT, 0x9c, 0, 0, },

	{ HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "mmc_mux",

	{ HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "sdio0_mux",

		CLK_SET_RATE_PARENT, 0x9c, 1, 0, },

	/* EMMC */

	{ HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m",