Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit bdc802dc authored by H. Peter Anvin's avatar H. Peter Anvin
Browse files

x86, cpu: Support the features flags in new CPUID leaf 7 



Intel has defined CPUID leaf 7 as the next set of feature flags (see
the AVX specification, version 007).  Add support for this new feature
flags word.

Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
LKML-Reference: <tip-*@vger.kernel.org>
parent 24da9c26

arch/x86/include/asm/cpufeature.h

+9 −4
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ 


#include <asm/required-features.h>



#define NCAPINTS	9	/* N 32-bit words worth of info */

#define NCAPINTS	10	/* N 32-bit words worth of info */



/*

 * Note: If the comment begins with a quoted string, that string is used
@@ -159,14 +159,14 @@ 


/*

 * Auxiliary flags: Linux defined - For features scattered in various

 * CPUID levels like 0x6, 0xA etc

 * CPUID levels like 0x6, 0xA etc, word 7

 */

#define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration */

#define X86_FEATURE_ARAT	(7*32+ 1) /* Always Running APIC Timer */

#define X86_FEATURE_CPB		(7*32+ 2) /* AMD Core Performance Boost */

#define X86_FEATURE_EPB		(7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */



/* Virtualization flags: Linux defined */

/* Virtualization flags: Linux defined, word 8 */

#define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */

#define X86_FEATURE_VNMI        (8*32+ 1) /* Intel Virtual NMI */

#define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */
@@ -177,6 +177,9 @@ 
#define X86_FEATURE_SVML	(8*32+7)  /* "svm_lock" AMD SVM locking MSR */

#define X86_FEATURE_NRIPS	(8*32+8)  /* "nrip_save" AMD SVM next_rip save */



/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */

#define X86_FEATURE_FSGSBASE	(9*32+0)  /* {RD/WR}{FS/GS}BASE instructions*/



#if defined(__KERNEL__) && !defined(__ASSEMBLY__)



#include <asm/asm.h>
@@ -197,7 +200,9 @@ extern const char * const x86_power_flags[32]; 
	   (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) ||	\

	   (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) ||	\

	   (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) ||	\

	   (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) )	\

	   (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ||	\

	   (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) ||	\

	   (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) )	\

	  ? 1 :								\

	 test_cpu_cap(c, bit))

arch/x86/include/asm/required-features.h

+2 −0
Original line number Diff line number Diff line
@@ -84,5 +84,7 @@ 
#define REQUIRED_MASK5	0

#define REQUIRED_MASK6	0

#define REQUIRED_MASK7	0

#define REQUIRED_MASK8	0

#define REQUIRED_MASK9	0



#endif /* _ASM_X86_REQUIRED_FEATURES_H */

arch/x86/kernel/cpu/common.c

+10 −0
Original line number Diff line number Diff line
@@ -551,6 +551,16 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) 
		c->x86_capability[4] = excap;

	}



	/* Additional Intel-defined flags: level 0x00000007 */

	if (c->cpuid_level >= 0x00000007) {

		u32 eax, ebx, ecx, edx;



		cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);



		if (eax > 0)

			c->x86_capability[9] = ebx;

	}



	/* AMD-defined flags: level 0x80000001 */

	xlvl = cpuid_eax(0x80000000);

	c->extended_cpuid_level = xlvl;