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Commit bd6d85c2 authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS: For Cavium OCTEON handle hazards as per the R10000 handling. 



For Cavium CPU, we treat the same as R10000, in that all hazards
are dealt with in hardware.

Signed-off-by: default avatarTomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: default avatarPaul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 5b3b1688

arch/mips/include/asm/hazards.h

+2 −2
Original line number Original line Diff line number Diff line
@@ -42,7 +42,7 @@ ASMMACRO(_ehb, 
/*

/*

 * TLB hazards

 * TLB hazards

 */

 */

#if defined(CONFIG_CPU_MIPSR2)

#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_CAVIUM_OCTEON)





/*

/*

 * MIPSR2 defines ehb for hazard avoidance

 * MIPSR2 defines ehb for hazard avoidance
@@ -138,7 +138,7 @@ do { \ 
		__instruction_hazard();					\

		__instruction_hazard();					\

} while (0)

} while (0)





#elif defined(CONFIG_CPU_R10000)

#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON)





/*

/*

 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.

 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.