+3
−1
Loading
Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more
The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus the IPU2 reset line and multi core CPU reset/enable bits. Signed-off-by:Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by:
Stephen Warren <swarren@nvidia.com> Reviewed-by:
Marek Vasut <marex@denx.de> Reviewed-by:
Pavel Machek <pavel@ucw.cz> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>