Merge "ARM: dts: msm: add dynamic-power-coefficient property for Kona" (bcdadd8b) · Commits · e / devices / android_kernel_fairphone_FP4

arch/arm/kernel/irq.c

+10 −1

Original line number	Diff line number	Diff line
		@@ -37,6 +37,7 @@
		#include <linux/kallsyms.h>
		#include <linux/proc_fs.h>
		#include <linux/export.h>
		#include <linux/cpumask.h>

		#include <asm/hardware/cache-l2x0.h>
		#include <asm/hardware/cache-uniphier.h>
		@@ -117,6 +118,7 @@ static bool migrate_one_irq(struct irq_desc *desc)
		const struct cpumask *affinity = irq_data_get_affinity_mask(d);
		struct irq_chip *c;
		bool ret = false;
		struct cpumask available_cpus;

		/*
		* If this is a per-CPU interrupt, or the affinity does not
		@@ -125,7 +127,14 @@ static bool migrate_one_irq(struct irq_desc *desc)
		if (irqd_is_per_cpu(d) \|\| !cpumask_test_cpu(smp_processor_id(), affinity))
		return false;

		cpumask_copy(&available_cpus, affinity);
		cpumask_andnot(&available_cpus, &available_cpus, cpu_isolated_mask);
		affinity = &available_cpus;

		if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
		cpumask_andnot(&available_cpus, cpu_online_mask,
		cpu_isolated_mask);
		if (cpumask_empty(affinity))
		affinity = cpu_online_mask;
		ret = true;
		}

arch/arm64/boot/dts/qcom/kona.dtsi

+8 −0

Original line number	Diff line number	Diff line
		@@ -48,6 +48,7 @@
		next-level-cache = <&L2_0>;
		qcom,freq-domain = <&cpufreq_hw 0 4>;
		capacity-dmips-mhz = <1024>;
		dynamic-power-coefficient = <100>;
		L2_0: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x20000>;
		@@ -72,6 +73,7 @@
		next-level-cache = <&L2_1>;
		qcom,freq-domain = <&cpufreq_hw 0 4>;
		capacity-dmips-mhz = <1024>;
		dynamic-power-coefficient = <100>;
		L2_1: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x20000>;
		@@ -90,6 +92,7 @@
		next-level-cache = <&L2_2>;
		qcom,freq-domain = <&cpufreq_hw 0 4>;
		capacity-dmips-mhz = <1024>;
		dynamic-power-coefficient = <100>;
		L2_2: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x20000>;
		@@ -108,6 +111,7 @@
		next-level-cache = <&L2_3>;
		qcom,freq-domain = <&cpufreq_hw 0 4>;
		capacity-dmips-mhz = <1024>;
		dynamic-power-coefficient = <100>;
		L2_3: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x20000>;
		@@ -126,6 +130,7 @@
		next-level-cache = <&L2_4>;
		qcom,freq-domain = <&cpufreq_hw 1 4>;
		capacity-dmips-mhz = <1894>;
		dynamic-power-coefficient = <374>;
		L2_4: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x20000>;
		@@ -144,6 +149,7 @@
		next-level-cache = <&L2_5>;
		qcom,freq-domain = <&cpufreq_hw 1 4>;
		capacity-dmips-mhz = <1894>;
		dynamic-power-coefficient = <374>;
		L2_5: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x20000>;
		@@ -162,6 +168,7 @@
		next-level-cache = <&L2_6>;
		qcom,freq-domain = <&cpufreq_hw 1 4>;
		capacity-dmips-mhz = <1894>;
		dynamic-power-coefficient = <374>;
		L2_6: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x20000>;
		@@ -180,6 +187,7 @@
		next-level-cache = <&L2_7>;
		qcom,freq-domain = <&cpufreq_hw 2 4>;
		capacity-dmips-mhz = <1894>;
		dynamic-power-coefficient = <431>;
		L2_7: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x80000>;

arch/arm64/configs/vendor/kona-perf_defconfig

+4 −0

Original line number	Diff line number	Diff line
		@@ -5,6 +5,7 @@ CONFIG_NO_HZ=y
		CONFIG_HIGH_RES_TIMERS=y
		CONFIG_PREEMPT=y
		CONFIG_IRQ_TIME_ACCOUNTING=y
		CONFIG_SCHED_WALT=y
		CONFIG_TASKSTATS=y
		CONFIG_TASK_XACCT=y
		CONFIG_TASK_IO_ACCOUNTING=y
		@@ -21,10 +22,12 @@ CONFIG_CGROUP_FREEZER=y
		CONFIG_CPUSETS=y
		CONFIG_CGROUP_CPUACCT=y
		CONFIG_CGROUP_BPF=y
		CONFIG_SCHED_CORE_CTL=y
		CONFIG_NAMESPACES=y
		# CONFIG_UTS_NS is not set
		# CONFIG_PID_NS is not set
		CONFIG_SCHED_AUTOGROUP=y
		CONFIG_SCHED_TUNE=y
		CONFIG_BLK_DEV_INITRD=y
		# CONFIG_RD_XZ is not set
		# CONFIG_RD_LZO is not set
		@@ -61,6 +64,7 @@ CONFIG_PM_AUTOSLEEP=y
		CONFIG_PM_WAKELOCKS=y
		CONFIG_PM_WAKELOCKS_LIMIT=0
		# CONFIG_PM_WAKELOCKS_GC is not set
		CONFIG_ENERGY_MODEL=y
		CONFIG_CPU_IDLE=y
		CONFIG_ARM_CPUIDLE=y
		CONFIG_CPU_FREQ=y

arch/arm64/configs/vendor/kona_defconfig

+4 −0

Original line number	Diff line number	Diff line
		@@ -4,6 +4,7 @@ CONFIG_NO_HZ=y
		CONFIG_HIGH_RES_TIMERS=y
		CONFIG_PREEMPT=y
		CONFIG_IRQ_TIME_ACCOUNTING=y
		CONFIG_SCHED_WALT=y
		CONFIG_TASKSTATS=y
		CONFIG_TASK_XACCT=y
		CONFIG_TASK_IO_ACCOUNTING=y
		@@ -21,10 +22,12 @@ CONFIG_CPUSETS=y
		CONFIG_CGROUP_CPUACCT=y
		CONFIG_CGROUP_BPF=y
		CONFIG_CGROUP_DEBUG=y
		CONFIG_SCHED_CORE_CTL=y
		CONFIG_NAMESPACES=y
		# CONFIG_UTS_NS is not set
		# CONFIG_PID_NS is not set
		CONFIG_SCHED_AUTOGROUP=y
		CONFIG_SCHED_TUNE=y
		CONFIG_BLK_DEV_INITRD=y
		# CONFIG_RD_XZ is not set
		# CONFIG_RD_LZO is not set
		@@ -62,6 +65,7 @@ CONFIG_PM_WAKELOCKS=y
		CONFIG_PM_WAKELOCKS_LIMIT=0
		# CONFIG_PM_WAKELOCKS_GC is not set
		CONFIG_PM_DEBUG=y
		CONFIG_ENERGY_MODEL=y
		CONFIG_CPU_IDLE=y
		CONFIG_ARM_CPUIDLE=y
		CONFIG_CPU_FREQ=y

drivers/base/core.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -716,6 +716,11 @@ int lock_device_hotplug_sysfs(void)
		return restart_syscall();
		}

		void lock_device_hotplug_assert(void)
		{
		lockdep_assert_held(&device_hotplug_lock);
		}

		#ifdef CONFIG_BLOCK
		static inline int device_is_not_partition(struct device *dev)
		{