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Commit bcc24fb4 authored by Jesse Barnes's avatar Jesse Barnes Committed by Eric Anholt
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drm/i915: increase default latency constant (v2 w/comment) 



Some i915/i945 platforms have a fairly high memory latency in certain
situations, so increase our constant a bit to avoid FIFO underruns.
The effect should be positive on other platforms as well; we'll have a
bit more insurance against a busy memory subsystem due to the extra
FIFO entries.

Fixes fdo bug #23368.  Needed for 2.6.31.

Tested-by: default avatarSven Arvidsson <sa@whiz.se>
Tested-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent 37d0892c

drivers/gpu/drm/i915/intel_display.c

+15 −1
Original line number Diff line number Diff line
@@ -2005,7 +2005,21 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock, 
	return;

}



const static int latency_ns = 3000; /* default for non-igd platforms */

/*

 * Latency for FIFO fetches is dependent on several factors:

 *   - memory configuration (speed, channels)

 *   - chipset

 *   - current MCH state

 * It can be fairly high in some situations, so here we assume a fairly

 * pessimal value.  It's a tradeoff between extra memory fetches (if we

 * set this value too high, the FIFO will fetch frequently to stay full)

 * and power consumption (set it too low to save power and we might see

 * FIFO underruns and display "flicker").

 *

 * A value of 5us seems to be a good balance; safe for very low end

 * platforms but not overly aggressive on lower latency configs.

 */

const static int latency_ns = 5000;



static int intel_get_fifo_size(struct drm_device *dev, int plane)

{