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Commit bcbdb6d0 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Protect gen7 irq_seqno_barrier with uncore lock 



Faced with sporadic machine hangs on gen7, that mimic the issue of
concurrent writes to the same cacheline and seem to start with
commit 9b9ed309 (drm/i915: Remove forcewake dance from seqno/irq
barrier on legacy gen6+), let us restore the spinlock around the mmio
read.

Fixes: 9b9ed309 (drm/i915: Remove forcewake dance from seqno/irq...)
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461744121-27051-1-git-send-email-chris@chris-wilson.co.uk


Tested-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
parent 19ab4ed3

drivers/gpu/drm/i915/intel_ringbuffer.c

+7 −1
Original line number Diff line number Diff line
@@ -1577,6 +1577,8 @@ pc_render_add_request(struct drm_i915_gem_request *req) 
static void

gen6_seqno_barrier(struct intel_engine_cs *engine)

{

	struct drm_i915_private *dev_priv = engine->dev->dev_private;



	/* Workaround to force correct ordering between irq and seqno writes on

	 * ivb (and maybe also on snb) by reading from a CS register (like

	 * ACTHD) before reading the status page.
@@ -1588,9 +1590,13 @@ gen6_seqno_barrier(struct intel_engine_cs *engine) 
	 * the write time to land, but that would incur a delay after every

	 * batch i.e. much more frequent than a delay when waiting for the

	 * interrupt (with the same net latency).

	 *

	 * Also note that to prevent whole machine hangs on gen7, we have to

	 * take the spinlock to guard against concurrent cacheline access.

	 */

	struct drm_i915_private *dev_priv = engine->dev->dev_private;

	spin_lock_irq(&dev_priv->uncore.lock);

	POSTING_READ_FW(RING_ACTHD(engine->mmio_base));

	spin_unlock_irq(&dev_priv->uncore.lock);

}



static u32