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Commit bc6a1c85 authored by Chuanxiao Dong's avatar Chuanxiao Dong Committed by Zhenyu Wang
Browse files

drm/i915/gvt: optimize the inhibit context mmio load 



For the inhibit ctx, load all mmio in render mmio list
into HW by MMIO write for ctx initialization.

For the none-inhibit ctx, only load the render mmio which
is not in_context into HW by MMIO write. Skip the MMIO write
for in_context mmio as context image will load it.

Signed-off-by: default avatarChuanxiao Dong <chuanxiao.dong@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 6e27d514

drivers/gpu/drm/i915/gvt/render.c

+17 −0
Original line number Diff line number Diff line
@@ -236,12 +236,18 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id) 
	}

}



#define CTX_CONTEXT_CONTROL_VAL	0x03



void intel_gvt_load_render_mmio(struct intel_vgpu *vgpu, int ring_id)

{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	struct render_mmio *mmio;

	u32 v;

	int i, array_size;

	u32 *reg_state = vgpu->shadow_ctx->engine[ring_id].lrc_reg_state;

	u32 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL];

	u32 inhibit_mask =

		_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);



	if (IS_SKYLAKE(vgpu->gvt->dev_priv)) {

		mmio = gen9_render_mmio_list;
@@ -257,6 +263,17 @@ void intel_gvt_load_render_mmio(struct intel_vgpu *vgpu, int ring_id) 
			continue;



		mmio->value = I915_READ(mmio->reg);



		/*

		 * if it is an inhibit context, load in_context mmio

		 * into HW by mmio write. If it is not, skip this mmio

		 * write.

		 */

		if (mmio->in_context &&

				((ctx_ctrl & inhibit_mask) != inhibit_mask) &&

				i915.enable_execlists)

			continue;



		if (mmio->mask)

			v = vgpu_vreg(vgpu, mmio->reg) | (mmio->mask << 16);

		else