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Commit bc30eea9 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "soc: swr-mstr: Add node to disable clk switch for rx master"

parents 0f652c84 687f9821

soc/swr-mstr-ctrl.c

+10 −3
Original line number Diff line number Diff line
@@ -1341,7 +1341,7 @@ static void swrm_apply_port_config(struct swr_master *master) 
	dev_dbg(swrm->dev, "%s: enter bank: %d master_ports: %d\n",

		__func__, bank, master->num_port);





	if (!swrm->disable_div2_clk_switch)

		swrm_cmd_fifo_wr_cmd(swrm, 0x01, 0xF, 0x00,

				SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(bank));
@@ -2648,6 +2648,7 @@ static int swrm_probe(struct platform_device *pdev) 
	swrm->state = SWR_MSTR_UP;

	swrm->ipc_wakeup = false;

	swrm->ipc_wakeup_triggered = false;

	swrm->disable_div2_clk_switch = FALSE;

	init_completion(&swrm->reset);

	init_completion(&swrm->broadcast);

	init_completion(&swrm->clk_off_complete);
@@ -2669,6 +2670,12 @@ static int swrm_probe(struct platform_device *pdev) 
	for (i = 0 ; i < SWR_MSTR_PORT_LEN; i++)

		INIT_LIST_HEAD(&swrm->mport_cfg[i].port_req_list);



	if (of_property_read_u32(pdev->dev.of_node,

			"qcom,disable-div2-clk-switch",

			&swrm->disable_div2_clk_switch)) {

		swrm->disable_div2_clk_switch = FALSE;

	}



	/* Register LPASS core hw vote */

	lpass_core_hw_vote = devm_clk_get(&pdev->dev, "lpass_core_hw_vote");

	if (IS_ERR(lpass_core_hw_vote)) {

soc/swr-mstr-ctrl.h

+1 −0
Original line number Diff line number Diff line
@@ -180,6 +180,7 @@ struct swr_mstr_ctrl { 
	int hw_core_clk_en;

	int aud_core_clk_en;

	int clk_src;

	u32 disable_div2_clk_switch;

#ifdef CONFIG_DEBUG_FS

	struct dentry *debugfs_swrm_dent;

	struct dentry *debugfs_peek;