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Commit bc27b7d3 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Use DP_LINK_RATE_SET whenever possible 



Drop the gen9 checks from the code and issue DP_LINK_RATE_SET whenever
the sink reports to support it.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarSonika Jindal <sonika.jindal@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 50fec21a

drivers/gpu/drm/i915/intel_dp.c

+7 −6
Original line number Diff line number Diff line
@@ -1371,14 +1371,15 @@ intel_dp_compute_config(struct intel_encoder *encoder, 


	intel_dp->lane_count = lane_count;



	intel_dp->link_bw =

		drm_dp_link_rate_to_bw_code(supported_rates[clock]);



	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {

	if (intel_dp->num_supported_rates) {

		intel_dp->link_bw = 0;

		intel_dp->rate_select =

			rate_to_index(supported_rates[clock],

				      intel_dp->supported_rates);

		intel_dp->link_bw = 0;

	} else {

		intel_dp->link_bw =

			drm_dp_link_rate_to_bw_code(supported_rates[clock]);

		intel_dp->rate_select = 0;

	}



	pipe_config->pipe_bpp = bpp;
@@ -3492,7 +3493,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) 
	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))

		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;

	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);

	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0])

	if (intel_dp->num_supported_rates)

		drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,

				&intel_dp->rate_select, 1);