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Commit bc0f566a authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Linus Walleij
Browse files

pinctrl: sunxi: fix nand0 function name for sun8i 



In sun4/5/6/7i, all the pin function related to NAND0 controller is
named "nand0". However, in sun8i, some of the functions are named as
"nand". This patch renamed them to "nand0", for the consistency.

Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.xyz>
Acked-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent cf9a2f63

drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c

+3 −3
Original line number Diff line number Diff line
@@ -180,17 +180,17 @@ static const struct sunxi_desc_pin sun8i_a23_pins[] = { 
	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "nand"),		/* DQ6 */

		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ6 */

		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D6 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "nand"),		/* DQ7 */

		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ7 */

		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D7 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "nand"),		/* DQS */

		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQS */

		  SUNXI_FUNCTION(0x3, "mmc2")),		/* RST */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c

+3 −3
Original line number Diff line number Diff line
@@ -140,17 +140,17 @@ static const struct sunxi_desc_pin sun8i_a33_pins[] = { 
	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "nand"),		/* DQ6 */

		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ6 */

		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D6 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "nand"),		/* DQ7 */

		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ7 */

		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D7 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "nand"),		/* DQS */

		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQS */

		  SUNXI_FUNCTION(0x3, "mmc2")),		/* RST */

	/* Hole */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),

drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c

+3 −3
Original line number Diff line number Diff line
@@ -219,17 +219,17 @@ static const struct sunxi_desc_pin sun8i_h3_pins[] = { 
	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "nand"),		/* DQ6 */

		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ6 */

		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D6 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "nand"),		/* DQ7 */

		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ7 */

		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D7 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "nand"),		/* DQS */

		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQS */

		  SUNXI_FUNCTION(0x3, "mmc2")),		/* RST */

	/* Hole */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),