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Commit bbaacfdc authored by Neeraj Soni's avatar Neeraj Soni
Browse files

ARM: dts: msm: Add inline crypto register details 

New FBE framework parses crypto engine details from host
controller node. Add this for sdcc host controller.

Change-Id: I0ccf93e1601a78b9ca676d0476ce1a82baaf64fb
parent f2af7a74

qcom/bengal.dtsi

+3 −28
Original line number Diff line number Diff line
@@ -1345,40 +1345,15 @@ 
		};

	};



	sdcc1_ice: sdcc1ice@4748000 {

		compatible = "qcom,ice";

		reg = <0x4748000 0x8000>;

		qcom,enable-ice-clk;

		clock-names = "ice_core_clk_src", "ice_core_clk",

				"bus_clk", "iface_clk";

		clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK_SRC>,

			<&gcc GCC_SDCC1_ICE_CORE_CLK>,

			<&gcc GCC_SDCC1_AHB_CLK>,

			<&gcc GCC_SDCC1_APPS_CLK>;

		qcom,op-freq-hz = <300000000>, <0>, <0>, <0>;

		qcom,msm-bus,name = "sdcc_ice_noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<MSM_BUS_MASTER_AMPSS_M0

				MSM_BUS_SLAVE_SDCC_1 0 0>,    /* No vote */

				<MSM_BUS_MASTER_AMPSS_M0

				MSM_BUS_SLAVE_SDCC_1 1000 0>;

				/* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "sdcc";

	};



	sdhc_1: sdhci@4744000 {

		compatible = "qcom,sdhci-msm-v5", "qcom,sdhci-msm-cqe";

		reg = <0x4744000 0x1000>, <0x4745000 0x1000>;

		reg-names = "hc_mem", "cqhci_mem";

		reg = <0x4744000 0x1000>, <0x4745000 0x1000>,

		      <0x4748000 0x8000>;

		reg-names = "hc_mem", "cqhci_mem", "cqhci_ice";



		interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "hc_irq", "pwr_irq";

		sdhc-msm-crypto = <&sdcc1_ice>;



		qcom,bus-width = <8>;

		qcom,large-address-bus;