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Commit bba610e9 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add cpufreq hardware node for SCUBA"

parents 6e8fc615 b04b0615

qcom/scuba.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ 
			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			L2_0: l2-cache {

				compatible = "arm,arch-cache";

				cache-size = <0x80000>;
@@ -63,6 +64,7 @@ 
			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;



			L1_I_1: l1-icache {

				compatible = "arm,arch-cache";
@@ -83,6 +85,7 @@ 
			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;



			L1_I_2: l1-icache {

				compatible = "arm,arch-cache";
@@ -103,6 +106,7 @@ 
			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;



			L1_I_3: l1-icache {

				compatible = "arm,arch-cache";
@@ -984,6 +988,17 @@ 
		#clock-cells = <1>;

	};



	cpufreq_hw: qcom,cpufreq-hw {

		compatible = "qcom,cpufreq-hw";

		reg = <0xf521000 0x1400>;

		reg-names = "freq-domain0";

		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;

		clock-names = "xo", "alternate";

		qcom,no-accumulative-counter;

		qcom,max-lut-entries = <12>;

		#freq-domain-cells = <2>;

	};



	tcsr_mutex_block: syscon@00340000 {

		compatible = "syscon";

		reg = <0x340000 0x20000>;