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Commit bb768f28 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
Browse files

ARM: tegra: Add video decoder on Tegra20 



Add a device tree node for the Video Decoder Engine found on Tegra20
SoCs.

Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent f143bf34

arch/arm/boot/dts/tegra20.dtsi

+27 −0
Original line number Original line Diff line number Diff line
@@ -16,6 +16,11 @@ 
		#address-cells = <1>;

		#address-cells = <1>;

		#size-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0x40000000 0x40000>;

		ranges = <0 0x40000000 0x40000>;



		vde_pool: vde {

			reg = <0x400 0x3fc00>;

			pool;

		};

	};

	};





	host1x@50000000 {

	host1x@50000000 {
@@ -258,6 +263,28 @@ 
		*/

		*/

	};

	};





	vde@6001a000 {

		compatible = "nvidia,tegra20-vde";

		reg = <0x6001a000 0x1000   /* Syntax Engine */

		       0x6001b000 0x1000   /* Video Bitstream Engine */

		       0x6001c000  0x100   /* Macroblock Engine */

		       0x6001c200  0x100   /* Post-processing Engine */

		       0x6001c400  0x100   /* Motion Compensation Engine */

		       0x6001c600  0x100   /* Transform Engine */

		       0x6001c800  0x100   /* Pixel prediction block */

		       0x6001ca00  0x100   /* Video DMA */

		       0x6001d800  0x300>; /* Video frame controls */

		reg-names = "sxe", "bsev", "mbe", "ppe", "mce",

			    "tfe", "ppb", "vdma", "frameid";

		iram = <&vde_pool>; /* IRAM region */

		interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */

			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */

			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */

		interrupt-names = "sync-token", "bsev", "sxe";

		clocks = <&tegra_car TEGRA20_CLK_VDE>;

		resets = <&tegra_car 61>;

	};



	apbmisc@70000800 {

	apbmisc@70000800 {

		compatible = "nvidia,tegra20-apbmisc";

		compatible = "nvidia,tegra20-apbmisc";

		reg = <0x70000800 0x64   /* Chip revision */

		reg = <0x70000800 0x64   /* Chip revision */