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Commit bb3d68c3 authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS: Add LDX and LWX instructions to uasm. 



Needed by Octeon II optimized TLB handlers.

Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Pachwork: https://patchwork.linux-mips.org/patch/1903/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent cc33ae43

arch/mips/include/asm/inst.h

+14 −0
Original line number Diff line number Diff line
@@ -72,6 +72,7 @@ enum spec2_op { 
enum spec3_op {

	ext_op, dextm_op, dextu_op, dext_op,

	ins_op, dinsm_op, dinsu_op, dins_op,

	lx_op = 0x0a,

	bshfl_op = 0x20,

	dbshfl_op = 0x24,

	rdhwr_op = 0x3b
@@ -178,6 +179,19 @@ enum mad_func { 
	nmadd_fp_op     = 0x0c, nmsub_fp_op     = 0x0e

};



/*

 * func field for special3 lx opcodes (Cavium Octeon).

 */

enum lx_func {

	lwx_op	= 0x00,

	lhx_op	= 0x04,

	lbux_op	= 0x06,

	ldx_op	= 0x08,

	lwux_op	= 0x10,

	lhux_op	= 0x14,

	lbx_op	= 0x16,

};



/*

 * Damn ...  bitfields depend from byteorder :-(

 */

arch/mips/include/asm/uasm.h

+4 −0
Original line number Diff line number Diff line
@@ -119,6 +119,8 @@ Ip_u2u1msbu3(_dinsm); 
Ip_u1(_syscall);

Ip_u1u2s3(_bbit0);

Ip_u1u2s3(_bbit1);

Ip_u3u1u2(_lwx);

Ip_u3u1u2(_ldx);



/* Handle labels. */

struct uasm_label {
@@ -156,6 +158,7 @@ static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ 
# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_dsubu(buf, rs, rt, rd)

# define UASM_i_LL(buf, rs, rt, off) uasm_i_lld(buf, rs, rt, off)

# define UASM_i_SC(buf, rs, rt, off) uasm_i_scd(buf, rs, rt, off)

# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_ldx(buf, rs, rt, rd)

#else

# define UASM_i_LW(buf, rs, rt, off) uasm_i_lw(buf, rs, rt, off)

# define UASM_i_SW(buf, rs, rt, off) uasm_i_sw(buf, rs, rt, off)
@@ -170,6 +173,7 @@ static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ 
# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_subu(buf, rs, rt, rd)

# define UASM_i_LL(buf, rs, rt, off) uasm_i_ll(buf, rs, rt, off)

# define UASM_i_SC(buf, rs, rt, off) uasm_i_sc(buf, rs, rt, off)

# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_lwx(buf, rs, rt, rd)

#endif



#define uasm_i_b(buf, off) uasm_i_beq(buf, 0, 0, off)

arch/mips/mm/uasm.c

+6 −1
Original line number Diff line number Diff line
@@ -68,7 +68,8 @@ enum opcode { 
	insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,

	insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp,

	insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,

	insn_dins, insn_dinsm, insn_syscall, insn_bbit0, insn_bbit1

	insn_dins, insn_dinsm, insn_syscall, insn_bbit0, insn_bbit1,

	insn_lwx, insn_ldx

};



struct insn {
@@ -146,6 +147,8 @@ static struct insn insn_table[] __uasminitdata = { 
	{ insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},

	{ insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },

	{ insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },

	{ insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },

	{ insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },

	{ insn_invalid, 0, 0 }

};
@@ -434,6 +437,8 @@ I_u2u1msb32u3(_dinsm); 
I_u1(_syscall);

I_u1u2s3(_bbit0);

I_u1u2s3(_bbit1);

I_u3u1u2(_lwx)

I_u3u1u2(_ldx)



#ifdef CONFIG_CPU_CAVIUM_OCTEON

#include <asm/octeon/octeon.h>