clk: qcom: gcc-kona: Enable safe config and HW_CTL for all RCGs (ba6d0af4) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/clk/qcom/gcc-kona.c

+74 −0

Original line number	Diff line number	Diff line
		@@ -292,6 +292,8 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_cpuss_ahb_clk_src",
		.parent_names = gcc_parent_names_0_ao,
		@@ -322,6 +324,8 @@ static struct clk_rcg2 gcc_gp1_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_1,
		.freq_tbl = ftbl_gcc_gp1_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_gp1_clk_src",
		.parent_names = gcc_parent_names_1,
		@@ -344,6 +348,8 @@ static struct clk_rcg2 gcc_gp2_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_1,
		.freq_tbl = ftbl_gcc_gp1_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_gp2_clk_src",
		.parent_names = gcc_parent_names_1,
		@@ -366,6 +372,8 @@ static struct clk_rcg2 gcc_gp3_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_1,
		.freq_tbl = ftbl_gcc_gp1_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_gp3_clk_src",
		.parent_names = gcc_parent_names_1,
		@@ -394,6 +402,8 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_2,
		.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_pcie_0_aux_clk_src",
		.parent_names = gcc_parent_names_2,
		@@ -413,6 +423,8 @@ static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_2,
		.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_pcie_1_aux_clk_src",
		.parent_names = gcc_parent_names_2,
		@@ -432,6 +444,8 @@ static struct clk_rcg2 gcc_pcie_2_aux_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_2,
		.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_pcie_2_aux_clk_src",
		.parent_names = gcc_parent_names_2,
		@@ -457,6 +471,8 @@ static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_pcie_phy_refgen_clk_src",
		.parent_names = gcc_parent_names_0_ao,
		@@ -484,6 +500,8 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_pdm2_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_pdm2_clk_src",
		.parent_names = gcc_parent_names_0,
		@@ -539,6 +557,8 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
		};

		@@ -562,6 +582,8 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
		};

		@@ -601,6 +623,8 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
		};

		@@ -624,6 +648,8 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
		};

		@@ -647,6 +673,8 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
		};

		@@ -670,6 +698,8 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
		};

		@@ -693,6 +723,8 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
		};

		@@ -716,6 +748,8 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
		};

		@@ -739,6 +773,8 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
		};

		@@ -762,6 +798,8 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
		};

		@@ -785,6 +823,8 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
		};

		@@ -808,6 +848,8 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
		};

		@@ -831,6 +873,8 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
		};

		@@ -854,6 +898,8 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
		};

		@@ -877,6 +923,8 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
		};

		@@ -900,6 +948,8 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
		};

		@@ -923,6 +973,8 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
		};

		@@ -946,6 +998,8 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
		};

		@@ -969,6 +1023,8 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
		};

		@@ -992,6 +1048,8 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
		};

		@@ -1011,6 +1069,8 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_4,
		.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_sdcc2_apps_clk_src",
		.parent_names = gcc_parent_names_4,
		@@ -1042,6 +1102,8 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_sdcc4_apps_clk_src",
		.parent_names = gcc_parent_names_0,
		@@ -1068,6 +1130,8 @@ static struct clk_rcg2 gcc_tsif_ref_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_5,
		.freq_tbl = ftbl_gcc_tsif_ref_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_tsif_ref_clk_src",
		.parent_names = gcc_parent_names_5,
		@@ -1318,6 +1382,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_usb30_prim_master_clk_src",
		.parent_names = gcc_parent_names_0,
		@@ -1341,6 +1406,8 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_usb30_prim_mock_utmi_clk_src",
		.parent_names = gcc_parent_names_0,
		@@ -1361,6 +1428,7 @@ static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_usb30_sec_master_clk_src",
		.parent_names = gcc_parent_names_0,
		@@ -1384,6 +1452,8 @@ static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_usb30_sec_mock_utmi_clk_src",
		.parent_names = gcc_parent_names_0,
		@@ -1403,6 +1473,8 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_2,
		.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_usb3_prim_phy_aux_clk_src",
		.parent_names = gcc_parent_names_2,
		@@ -1422,6 +1494,8 @@ static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_2,
		.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
		.enable_safe_config = true,
		.flags = HW_CLK_CTRL_MODE,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_usb3_sec_phy_aux_clk_src",
		.parent_names = gcc_parent_names_2,