Loading qcom/bengal-gpu.dtsi +89 −2 Original line number Diff line number Diff line Loading @@ -14,6 +14,11 @@ opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>; }; opp-950000000 { opp-hz = /bits/ 64 <950000000>; opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>; }; opp-900000000 { opp-hz = /bits/ 64 <900000000>; opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>; Loading Loading @@ -175,7 +180,7 @@ qcom,gpu-cx-ipeak@0 { qcom,gpu-cx-ipeak = <&cx_ipeak_lm 10>; qcom,gpu-cx-ipeak-freq = <980000000>; qcom,gpu-cx-ipeak-freq = <950000000>; }; qcom,gpu-cx-ipeak@1 { Loading Loading @@ -397,6 +402,88 @@ #address-cells = <1>; #size-cells = <0>; qcom,speed-bin = <200>; qcom,initial-pwrlevel = <6>; qcom,ca-target-pwrlevel = <5>; /* TURBO_L1 */ qcom,gpu-pwrlevel@0 { reg = <0>; qcom,gpu-freq = <950000000>; qcom,bus-freq = <11>; qcom,bus-min = <10>; qcom,bus-max = <11>; }; /* TURBO */ qcom,gpu-pwrlevel@1 { reg = <1>; qcom,gpu-freq = <900000000>; qcom,bus-freq = <11>; qcom,bus-min = <9>; qcom,bus-max = <11>; }; /* NOM_L1 */ qcom,gpu-pwrlevel@2 { reg = <2>; qcom,gpu-freq = <820000000>; qcom,bus-freq = <10>; qcom,bus-min = <9>; qcom,bus-max = <11>; }; /* NOM */ qcom,gpu-pwrlevel@3 { reg = <3>; qcom,gpu-freq = <745000000>; qcom,bus-freq = <9>; qcom,bus-min = <8>; qcom,bus-max = <10>; }; /* SVS_L1 */ qcom,gpu-pwrlevel@4 { reg = <4>; qcom,gpu-freq = <600000000>; qcom,bus-freq = <8>; qcom,bus-min = <7>; qcom,bus-max = <9>; }; /* SVS */ qcom,gpu-pwrlevel@5 { reg = <5>; qcom,gpu-freq = <465000000>; qcom,bus-freq = <7>; qcom,bus-min = <5>; qcom,bus-max = <8>; }; /* LOW SVS */ qcom,gpu-pwrlevel@6 { reg = <6>; qcom,gpu-freq = <320000000>; qcom,bus-freq = <4>; qcom,bus-min = <3>; qcom,bus-max = <5>; }; /* XO */ qcom,gpu-pwrlevel@7 { reg = <7>; qcom,gpu-freq = <0>; qcom,bus-freq = <0>; qcom,bus-min = <0>; qcom,bus-max = <0>; }; }; qcom,gpu-pwrlevels-3 { #address-cells = <1>; #size-cells = <0>; qcom,speed-bin = <157>; qcom,initial-pwrlevel = <3>; Loading Loading @@ -448,7 +535,7 @@ }; }; qcom,gpu-pwrlevels-3 { qcom,gpu-pwrlevels-4 { #address-cells = <1>; #size-cells = <0>; Loading Loading
qcom/bengal-gpu.dtsi +89 −2 Original line number Diff line number Diff line Loading @@ -14,6 +14,11 @@ opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>; }; opp-950000000 { opp-hz = /bits/ 64 <950000000>; opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>; }; opp-900000000 { opp-hz = /bits/ 64 <900000000>; opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>; Loading Loading @@ -175,7 +180,7 @@ qcom,gpu-cx-ipeak@0 { qcom,gpu-cx-ipeak = <&cx_ipeak_lm 10>; qcom,gpu-cx-ipeak-freq = <980000000>; qcom,gpu-cx-ipeak-freq = <950000000>; }; qcom,gpu-cx-ipeak@1 { Loading Loading @@ -397,6 +402,88 @@ #address-cells = <1>; #size-cells = <0>; qcom,speed-bin = <200>; qcom,initial-pwrlevel = <6>; qcom,ca-target-pwrlevel = <5>; /* TURBO_L1 */ qcom,gpu-pwrlevel@0 { reg = <0>; qcom,gpu-freq = <950000000>; qcom,bus-freq = <11>; qcom,bus-min = <10>; qcom,bus-max = <11>; }; /* TURBO */ qcom,gpu-pwrlevel@1 { reg = <1>; qcom,gpu-freq = <900000000>; qcom,bus-freq = <11>; qcom,bus-min = <9>; qcom,bus-max = <11>; }; /* NOM_L1 */ qcom,gpu-pwrlevel@2 { reg = <2>; qcom,gpu-freq = <820000000>; qcom,bus-freq = <10>; qcom,bus-min = <9>; qcom,bus-max = <11>; }; /* NOM */ qcom,gpu-pwrlevel@3 { reg = <3>; qcom,gpu-freq = <745000000>; qcom,bus-freq = <9>; qcom,bus-min = <8>; qcom,bus-max = <10>; }; /* SVS_L1 */ qcom,gpu-pwrlevel@4 { reg = <4>; qcom,gpu-freq = <600000000>; qcom,bus-freq = <8>; qcom,bus-min = <7>; qcom,bus-max = <9>; }; /* SVS */ qcom,gpu-pwrlevel@5 { reg = <5>; qcom,gpu-freq = <465000000>; qcom,bus-freq = <7>; qcom,bus-min = <5>; qcom,bus-max = <8>; }; /* LOW SVS */ qcom,gpu-pwrlevel@6 { reg = <6>; qcom,gpu-freq = <320000000>; qcom,bus-freq = <4>; qcom,bus-min = <3>; qcom,bus-max = <5>; }; /* XO */ qcom,gpu-pwrlevel@7 { reg = <7>; qcom,gpu-freq = <0>; qcom,bus-freq = <0>; qcom,bus-min = <0>; qcom,bus-max = <0>; }; }; qcom,gpu-pwrlevels-3 { #address-cells = <1>; #size-cells = <0>; qcom,speed-bin = <157>; qcom,initial-pwrlevel = <3>; Loading Loading @@ -448,7 +535,7 @@ }; }; qcom,gpu-pwrlevels-3 { qcom,gpu-pwrlevels-4 { #address-cells = <1>; #size-cells = <0>; Loading