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Commit b9fd799e authored by Rodrigo Vivi's avatar Rodrigo Vivi Committed by Ander Conselvan de Oliveira
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drm/i915/glk: Add missing bits to allow runtime pm suspend on GLK. 



Besides having the DMC firmware in place and loaded let's
handle runtime suspend and dc9 as we do for Broxton.

Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1481902946-18593-2-git-send-email-ander.conselvan.de.oliveira@intel.com
parent dbb28b5c

drivers/gpu/drm/i915/i915_drv.c

+6 −6
Original line number Diff line number Diff line
@@ -1471,7 +1471,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 


	intel_display_set_init_power(dev_priv, false);



	fw_csr = !IS_BROXTON(dev_priv) &&

	fw_csr = !IS_GEN9_LP(dev_priv) &&

		suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;

	/*

	 * In case of firmware assisted context save/restore don't manually
@@ -1484,7 +1484,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 
		intel_power_domains_suspend(dev_priv);



	ret = 0;

	if (IS_BROXTON(dev_priv))

	if (IS_GEN9_LP(dev_priv))

		bxt_enable_dc9(dev_priv);

	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))

		hsw_enable_pc8(dev_priv);
@@ -1692,7 +1692,7 @@ static int i915_drm_resume_early(struct drm_device *dev) 


	intel_uncore_early_sanitize(dev_priv, true);



	if (IS_BROXTON(dev_priv)) {

	if (IS_GEN9_LP(dev_priv)) {

		if (!dev_priv->suspended_to_idle)

			gen9_sanitize_dc_state(dev_priv);

		bxt_disable_dc9(dev_priv);
@@ -1702,7 +1702,7 @@ static int i915_drm_resume_early(struct drm_device *dev) 


	intel_uncore_sanitize(dev_priv);



	if (IS_BROXTON(dev_priv) ||

	if (IS_GEN9_LP(dev_priv) ||

	    !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))

		intel_power_domains_init_hw(dev_priv, true);
@@ -2326,7 +2326,7 @@ static int intel_runtime_suspend(struct device *kdev) 
	intel_runtime_pm_disable_interrupts(dev_priv);



	ret = 0;

	if (IS_BROXTON(dev_priv)) {

	if (IS_GEN9_LP(dev_priv)) {

		bxt_display_core_uninit(dev_priv);

		bxt_enable_dc9(dev_priv);

	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -2411,7 +2411,7 @@ static int intel_runtime_resume(struct device *kdev) 
	if (IS_GEN6(dev_priv))

		intel_init_pch_refclk(dev_priv);



	if (IS_BROXTON(dev_priv)) {

	if (IS_GEN9_LP(dev_priv)) {

		bxt_disable_dc9(dev_priv);

		bxt_display_core_init(dev_priv, true);

		if (dev_priv->csr.dmc_payload &&