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Commit b9a1077a authored by Dave Airlie's avatar Dave Airlie
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Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into drm-next 

Main pull req for 4.2.. I think there will be a secondary pull-req..
I'd like to land the hdcp support patches, since all the review
comments have been long since addressed, and they have been ready to
merge for a couple release cycles now other than the scm dependency
(which should be coming in through arm-soc tree for 4.2). So I am not
including them in this initial pull req to avoid merge ordering
issues.

Main highlights:

1) adreno a306 support (for apq8x16 and upcoming dragonboard 410c)
2) various dsi bits
3) various 64bit fixes (mostly warnings)
4) NV12MT support, pulled in via msm-next rather than drm-misc since
dependency on on regenerated envytools headers (but lgtm'd-by danvet)
5) random fixes and cleanups

* 'msm-next' of git://people.freedesktop.org/~robclark/linux: (36 commits)
  drm/msm: restart queued submits after hang
  drm/msm: fix timeout calculation
  drm/msm/hdmi: Use pinctrl in HDMI driver
  drm/msm/hdmi: Point to the right struct device
  drm/msm/mdp: Add support for more 32-bit RGB formats
  drm/msm: use __s32, __s64, __u32 and __u64 from linux/types.h for uabi
  drm/msm/atomic: Clean up planes in the error paths of .atomic_commit()
  drm/msm/mdp5: Always generate active-high sync signals for DSI
  drm/msm: dsi: fix compile errors when CONFIG_GPIOLIB=n
  drm/msm: use devm_gpiod_get_optional for optional reset gpio
  drm/msm/dsi: Separate PHY to another platform device
  drm/msm/dsi: Enable PLL driver in MSM DSI
  drm/msm/dsi: Add DSI PLL clock driver support
  drm/msm: use IS_ERR() to check regulator_get() return
  drm/msm: use IS_ERR() to check msm_ioremap() return
  drm/msm/mdp5: Wait for PP_DONE irq for command mode CRTC atomic commit
  drm/msm: Use customized function to wait for atomic commit done
  dt-bindings: Add MSM eDP controller documentation
  dt-bindings: Add MSM DSI controller documentation
  drm/msm: drop redundant debug output
  ...
parents 5c70c464 1a370be9

Documentation/devicetree/bindings/drm/msm/dsi.txt

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+120 −0
Original line number Diff line number Diff line 
Qualcomm Technologies Inc. adreno/snapdragon DSI output



DSI Controller:

Required properties:

- compatible:

  * "qcom,mdss-dsi-ctrl"

- reg: Physical base address and length of the registers of controller

- reg-names: The names of register regions. The following regions are required:

  * "dsi_ctrl"

- qcom,dsi-host-index: The ID of DSI controller hardware instance. This should

  be 0 or 1, since we have 2 DSI controllers at most for now.

- interrupts: The interrupt signal from the DSI block.

- power-domains: Should be <&mmcc MDSS_GDSC>.

- clocks: device clocks

  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.

- clock-names: the following clocks are required:

  * "bus_clk"

  * "byte_clk"

  * "core_clk"

  * "core_mmss_clk"

  * "iface_clk"

  * "mdp_core_clk"

  * "pixel_clk"

- vdd-supply: phandle to vdd regulator device node

- vddio-supply: phandle to vdd-io regulator device node

- vdda-supply: phandle to vdda regulator device node

- qcom,dsi-phy: phandle to DSI PHY device node



Optional properties:

- panel@0: Node of panel connected to this DSI controller.

  See files in Documentation/devicetree/bindings/panel/ for each supported

  panel.

- qcom,dual-panel-mode: Boolean value indicating if the DSI controller is

  driving a panel which needs 2 DSI links.

- qcom,master-panel: Boolean value indicating if the DSI controller is driving

  the master link of the 2-DSI panel.

- qcom,sync-dual-panel: Boolean value indicating if the DSI controller is

  driving a 2-DSI panel whose 2 links need receive command simultaneously.

- interrupt-parent: phandle to the MDP block if the interrupt signal is routed

  through MDP block



DSI PHY:

Required properties:

- compatible: Could be the following

  * "qcom,dsi-phy-28nm-hpm"

  * "qcom,dsi-phy-28nm-lp"

- reg: Physical base address and length of the registers of PLL, PHY and PHY

  regulator

- reg-names: The names of register regions. The following regions are required:

  * "dsi_pll"

  * "dsi_phy"

  * "dsi_phy_regulator"

- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should

  be 0 or 1, since we have 2 DSI PHYs at most for now.

- power-domains: Should be <&mmcc MDSS_GDSC>.

- clocks: device clocks

  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.

- clock-names: the following clocks are required:

  * "iface_clk"

- vddio-supply: phandle to vdd-io regulator device node



Example:

	mdss_dsi0: qcom,mdss_dsi@fd922800 {

		compatible = "qcom,mdss-dsi-ctrl";

		qcom,dsi-host-index = <0>;

		interrupt-parent = <&mdss_mdp>;

		interrupts = <4 0>;

		reg-names = "dsi_ctrl";

		reg = <0xfd922800 0x200>;

		power-domains = <&mmcc MDSS_GDSC>;

		clock-names =

			"bus_clk",

			"byte_clk",

			"core_clk",

			"core_mmss_clk",

			"iface_clk",

			"mdp_core_clk",

			"pixel_clk";

		clocks =

			<&mmcc MDSS_AXI_CLK>,

			<&mmcc MDSS_BYTE0_CLK>,

			<&mmcc MDSS_ESC0_CLK>,

			<&mmcc MMSS_MISC_AHB_CLK>,

			<&mmcc MDSS_AHB_CLK>,

			<&mmcc MDSS_MDP_CLK>,

			<&mmcc MDSS_PCLK0_CLK>;

		vdda-supply = <&pma8084_l2>;

		vdd-supply = <&pma8084_l22>;

		vddio-supply = <&pma8084_l12>;



		qcom,dsi-phy = <&mdss_dsi_phy0>;



		qcom,dual-panel-mode;

		qcom,master-panel;

		qcom,sync-dual-panel;



		panel: panel@0 {

			compatible = "sharp,lq101r1sx01";

			reg = <0>;

			link2 = <&secondary>;



			power-supply = <...>;

			backlight = <...>;

		};

	};



	mdss_dsi_phy0: qcom,mdss_dsi_phy@fd922a00 {

		compatible = "qcom,dsi-phy-28nm-hpm";

		qcom,dsi-phy-index = <0>;

		reg-names =

			"dsi_pll",

			"dsi_phy",

			"dsi_phy_regulator";

		reg =   <0xfd922a00 0xd4>,

			<0xfd922b00 0x2b0>,

			<0xfd922d80 0x7b>;

		clock-names = "iface_clk";

		clocks = <&mmcc MDSS_AHB_CLK>;

		vddio-supply = <&pma8084_l12>;

	};

Documentation/devicetree/bindings/drm/msm/edp.txt

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+60 −0
Original line number Diff line number Diff line 
Qualcomm Technologies Inc. adreno/snapdragon eDP output



Required properties:

- compatible:

  * "qcom,mdss-edp"

- reg: Physical base address and length of the registers of controller and PLL

- reg-names: The names of register regions. The following regions are required:

  * "edp"

  * "pll_base"

- interrupts: The interrupt signal from the eDP block.

- power-domains: Should be <&mmcc MDSS_GDSC>.

- clocks: device clocks

  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.

- clock-names: the following clocks are required:

  * "core_clk"

  * "iface_clk"

  * "mdp_core_clk"

  * "pixel_clk"

  * "link_clk"

- #clock-cells: The value should be 1.

- vdda-supply: phandle to vdda regulator device node

- lvl-vdd-supply: phandle to regulator device node which is used to supply power

  to HPD receiving chip

- panel-en-gpios: GPIO pin to supply power to panel.

- panel-hpd-gpios: GPIO pin used for eDP hpd.





Optional properties:

- interrupt-parent: phandle to the MDP block if the interrupt signal is routed

  through MDP block



Example:

	mdss_edp: qcom,mdss_edp@fd923400 {

			compatible = "qcom,mdss-edp";

			reg-names =

				"edp",

				"pll_base";

			reg =	<0xfd923400 0x700>,

				<0xfd923a00 0xd4>;

			interrupt-parent = <&mdss_mdp>;

			interrupts = <12 0>;

			power-domains = <&mmcc MDSS_GDSC>;

			clock-names =

				"core_clk",

				"pixel_clk",

				"iface_clk",

				"link_clk",

				"mdp_core_clk";

			clocks =

				<&mmcc MDSS_EDPAUX_CLK>,

				<&mmcc MDSS_EDPPIXEL_CLK>,

				<&mmcc MDSS_AHB_CLK>,

				<&mmcc MDSS_EDPLINK_CLK>,

				<&mmcc MDSS_MDP_CLK>;

			#clock-cells = <1>;

			vdda-supply = <&pma8084_l12>;

			lvl-vdd-supply = <&lvl_vreg>;

			panel-en-gpios = <&tlmm 137 0>;

			panel-hpd-gpios = <&tlmm 103 0>;

	};

Documentation/devicetree/bindings/drm/msm/hdmi.txt

+6 −0
Original line number Diff line number Diff line
@@ -20,6 +20,9 @@ Required properties: 
Optional properties:

- qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin

- qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin

- pinctrl-names: the pin control state names; should contain "default"

- pinctrl-0: the default pinctrl state (active)

- pinctrl-1: the "sleep" pinctrl state



Example:
@@ -44,5 +47,8 @@ Example: 
		qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>;

		core-vdda-supply = <&pm8921_hdmi_mvs>;

		hdmi-mux-supply = <&ext_3p3v>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&hpd_active  &ddc_active  &cec_active>;

		pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;

	};

};

drivers/gpu/drm/drm_crtc.c

+18 −0
Original line number Diff line number Diff line
@@ -3255,6 +3255,24 @@ static int framebuffer_check(const struct drm_mode_fb_cmd2 *r) 
				      r->modifier[i], i);

			return -EINVAL;

		}



		/* modifier specific checks: */

		switch (r->modifier[i]) {

		case DRM_FORMAT_MOD_SAMSUNG_64_32_TILE:

			/* NOTE: the pitch restriction may be lifted later if it turns

			 * out that no hw has this restriction:

			 */

			if (r->pixel_format != DRM_FORMAT_NV12 ||

					width % 128 || height % 32 ||

					r->pitches[i] % 128) {

				DRM_DEBUG_KMS("bad modifier data for plane %d\n", i);

				return -EINVAL;

			}

			break;



		default:

			break;

		}

	}



	for (i = num_planes; i < 4; i++) {

drivers/gpu/drm/msm/Kconfig

+7 −0
Original line number Diff line number Diff line
@@ -46,3 +46,10 @@ config DRM_MSM_DSI 
	  Choose this option if you have a need for MIPI DSI connector

	  support.



config DRM_MSM_DSI_PLL

	bool "Enable DSI PLL driver in MSM DRM"

	depends on DRM_MSM_DSI && COMMON_CLK

	default y

	help

	  Choose this option to enable DSI PLL driver which provides DSI

	  source clocks under common clock framework.