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Commit b9687b48 authored by Sunil Goutham's avatar Sunil Goutham Committed by David S. Miller
Browse files

net: thunderx: Enable CQE count threshold interrupt 



This feature is introduced in pass-2 chip and with this CQ interrupt
coalescing will work based on both timer and count.

Signed-off-by: default avatarSunil Goutham <sgoutham@cavium.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 40fb5f8a

drivers/net/ethernet/cavium/thunder/nicvf_queues.c

+1 −1
Original line number Diff line number Diff line
@@ -299,7 +299,7 @@ static int nicvf_init_cmp_queue(struct nicvf *nic, 
		return err;



	cq->desc = cq->dmem.base;

	cq->thresh = CMP_QUEUE_CQE_THRESH;

	cq->thresh = pass1_silicon(nic->pdev) ? 0 : CMP_QUEUE_CQE_THRESH;

	nic->cq_coalesce_usecs = (CMP_QUEUE_TIMER_THRESH * 0.05) - 1;



	return 0;

drivers/net/ethernet/cavium/thunder/nicvf_queues.h

+1 −1
Original line number Diff line number Diff line
@@ -75,7 +75,7 @@ 
 */

#define CMP_QSIZE		CMP_QUEUE_SIZE2

#define CMP_QUEUE_LEN		(1ULL << (CMP_QSIZE + 10))

#define CMP_QUEUE_CQE_THRESH	0

#define CMP_QUEUE_CQE_THRESH	(NAPI_POLL_WEIGHT / 2)

#define CMP_QUEUE_TIMER_THRESH	80 /* ~2usec */



#define RBDR_SIZE		RBDR_SIZE0