media: dvb_frontends: fix kernel-doc macros (b95b0c98) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h

+6 −6

Original line number	Diff line number	Diff line
		@@ -52,7 +52,7 @@ struct i2c_device_addr {
		};


		/**
		/*
		* \def IS_I2C_10BIT( addr )
		* \brief Determine if I2C address 'addr' is a 10 bits address or not.
		* \param addr The I2C address.
		@@ -67,7 +67,7 @@ struct i2c_device_addr {
		Exported FUNCTIONS
		------------------------------------------------------------------------------*/

		/**
		/*
		* \fn drxbsp_i2c_init()
		* \brief Initialize I2C communication module.
		* \return drx_status_t Return status.
		@@ -76,7 +76,7 @@ Exported FUNCTIONS
		*/
		drx_status_t drxbsp_i2c_init(void);

		/**
		/*
		* \fn drxbsp_i2c_term()
		* \brief Terminate I2C communication module.
		* \return drx_status_t Return status.
		@@ -85,7 +85,7 @@ Exported FUNCTIONS
		*/
		drx_status_t drxbsp_i2c_term(void);

		/**
		/*
		* \fn drx_status_t drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr,
		* u16 w_count,
		* u8 *wData,
		@@ -121,7 +121,7 @@ Exported FUNCTIONS
		struct i2c_device_addr *r_dev_addr,
		u16 r_count, u8 *r_data);

		/**
		/*
		* \fn drxbsp_i2c_error_text()
		* \brief Returns a human readable error.
		* Counter part of numerical drx_i2c_error_g.
		@@ -130,7 +130,7 @@ Exported FUNCTIONS
		*/
		char *drxbsp_i2c_error_text(void);

		/**
		/*
		* \var drx_i2c_error_g;
		* \brief I2C specific error codes, platform dependent.
		*/

drivers/media/dvb-frontends/drx39xyj/drx_driver.h

+439 −439

File changed.

Preview size limit exceeded, changes collapsed.

drivers/media/dvb-frontends/drx39xyj/drxj.h

+110 −110

Original line number	Diff line number	Diff line
		@@ -69,15 +69,15 @@ TYPEDEFS

		struct drxjscu_cmd {
		u16 command;
		/*< Command number /
		/< Command number /
		u16 parameter_len;
		/*< Data length in byte /
		/< Data length in byte /
		u16 result_len;
		/*< result length in byte /
		/< result length in byte /
		u16 *parameter;
		/*< General purpous param /
		/< General purpous param /
		u16 *result;
		/*< General purpous param /};
		/< General purpous param /};

		/============================================================================/
		/============================================================================/
		@@ -130,7 +130,7 @@ TYPEDEFS

		DRXJ_CFG_MAX /* dummy, never to be used */};

		/**
		/*
		* /struct enum drxj_cfg_smart_ant_io * smart antenna i/o.
		*/
		enum drxj_cfg_smart_ant_io {
		@@ -138,7 +138,7 @@ enum drxj_cfg_smart_ant_io {
		DRXJ_SMT_ANT_INPUT
		};

		/**
		/*
		* /struct struct drxj_cfg_smart_ant * Set smart antenna.
		*/
		struct drxj_cfg_smart_ant {
		@@ -146,7 +146,7 @@ enum drxj_cfg_smart_ant_io {
		u16 ctrl_data;
		};

		/**
		/*
		* /struct DRXJAGCSTATUS_t
		* AGC status information from the DRXJ-IQM-AF.
		*/
		@@ -158,7 +158,7 @@ struct drxj_agc_status {

		/* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */

		/**
		/*
		* /struct enum drxj_agc_ctrl_mode * Available AGCs modes in the DRXJ.
		*/
		enum drxj_agc_ctrl_mode {
		@@ -166,7 +166,7 @@ struct drxj_agc_status {
		DRX_AGC_CTRL_USER,
		DRX_AGC_CTRL_OFF};

		/**
		/*
		* /struct struct drxj_cfg_agc * Generic interface for all AGCs present on the DRXJ.
		*/
		struct drxj_cfg_agc {
		@@ -182,7 +182,7 @@ struct drxj_agc_status {

		/* DRXJ_CFG_PRE_SAW */

		/**
		/*
		* /struct struct drxj_cfg_pre_saw * Interface to configure pre SAW sense.
		*/
		struct drxj_cfg_pre_saw {
		@@ -192,14 +192,14 @@ struct drxj_agc_status {

		/* DRXJ_CFG_AFE_GAIN */

		/**
		/*
		* /struct struct drxj_cfg_afe_gain * Interface to configure gain of AFE (LNA + PGA).
		*/
		struct drxj_cfg_afe_gain {
		enum drx_standard standard; /* standard to which these settings apply */
		u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */};

		/**
		/*
		* /struct drxjrs_errors
		* Available failure information in DRXJ_FEC_RS.
		*
		@@ -208,25 +208,25 @@ struct drxj_agc_status {
		*/
		struct drxjrs_errors {
		u16 nr_bit_errors;
		/*< no of pre RS bit errors /
		/< no of pre RS bit errors /
		u16 nr_symbol_errors;
		/*< no of pre RS symbol errors /
		/< no of pre RS symbol errors /
		u16 nr_packet_errors;
		/*< no of pre RS packet errors /
		/< no of pre RS packet errors /
		u16 nr_failures;
		/*< no of post RS failures to decode /
		/< no of post RS failures to decode /
		u16 nr_snc_par_fail_count;
		/*< no of post RS bit erros /
		/< no of post RS bit erros /
		};

		/**
		/*
		* /struct struct drxj_cfg_vsb_misc * symbol error rate
		*/
		struct drxj_cfg_vsb_misc {
		u32 symb_error;
		/*< symbol error rate sps /};
		/< symbol error rate sps /};

		/**
		/*
		* /enum enum drxj_mpeg_output_clock_rate * Mpeg output clock rate.
		*
		*/
		@@ -234,7 +234,7 @@ struct drxj_agc_status {
		DRXJ_MPEG_START_WIDTH_1CLKCYC,
		DRXJ_MPEG_START_WIDTH_8CLKCYC};

		/**
		/*
		* /enum enum drxj_mpeg_output_clock_rate * Mpeg output clock rate.
		*
		*/
		@@ -247,20 +247,20 @@ struct drxj_agc_status {
		DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K,
		DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K};

		/**
		/*
		* /struct DRXJCfgMisc_t
		* Change TEI bit of MPEG output
		* reverse MPEG output bit order
		* set MPEG output clock rate
		*/
		struct drxj_cfg_mpeg_output_misc {
		bool disable_tei_handling; /*< if true pass (not change) TEI bit /
		bool bit_reverse_mpeg_outout; /*< if true, parallel: msb on MD0; serial: lsb out first /
		bool disable_tei_handling; /< if true pass (not change) TEI bit /
		bool bit_reverse_mpeg_outout; /< if true, parallel: msb on MD0; serial: lsb out first /
		enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate;
		/*< set MPEG output clock rate that overwirtes the derived one from symbol rate /
		enum drxj_mpeg_start_width mpeg_start_width; /*< set MPEG output start width /};
		/< set MPEG output clock rate that overwirtes the derived one from symbol rate /
		enum drxj_mpeg_start_width mpeg_start_width; /< set MPEG output start width /};

		/**
		/*
		* /enum enum drxj_xtal_freq * Supported external crystal reference frequency.
		*/
		enum drxj_xtal_freq {
		@@ -269,21 +269,21 @@ struct drxj_agc_status {
		DRXJ_XTAL_FREQ_20P25MHZ,
		DRXJ_XTAL_FREQ_4MHZ};

		/**
		/*
		* /enum enum drxj_xtal_freq * Supported external crystal reference frequency.
		*/
		enum drxji2c_speed {
		DRXJ_I2C_SPEED_400KBPS,
		DRXJ_I2C_SPEED_100KBPS};

		/**
		/*
		* /struct struct drxj_cfg_hw_cfg * Get hw configuration, such as crystal reference frequency, I2C speed, etc...
		*/
		struct drxj_cfg_hw_cfg {
		enum drxj_xtal_freq xtal_freq;
		/*< crystal reference frequency /
		/< crystal reference frequency /
		enum drxji2c_speed i2c_speed;
		/*< 100 or 400 kbps /};
		/< 100 or 400 kbps /};

		/*
		* DRXJ_CFG_ATV_MISC
		@@ -352,7 +352,7 @@ struct drxj_cfg_oob_misc {
		* DRXJ_CFG_ATV_OUTPUT
		*/

		/**
		/*
		* /enum DRXJAttenuation_t
		* Attenuation setting for SIF AGC.
		*
		@@ -363,7 +363,7 @@ struct drxj_cfg_oob_misc {
		DRXJ_SIF_ATTENUATION_6DB,
		DRXJ_SIF_ATTENUATION_9DB};

		/**
		/*
		* /struct struct drxj_cfg_atv_output * SIF attenuation setting.
		*
		*/
		@@ -398,7 +398,7 @@ struct drxj_cfg_atv_output {
		/============================================================================/

		/========================================/
		/**
		/*
		* /struct struct drxj_data * DRXJ specific attributes.
		*
		* Global data container for DRXJ specific data.
		@@ -406,93 +406,93 @@ struct drxj_cfg_atv_output {
		*/
		struct drxj_data {
		/* device capabilties (determined during drx_open()) */
		bool has_lna; /*< true if LNA (aka PGA) present /
		bool has_oob; /*< true if OOB supported /
		bool has_ntsc; /*< true if NTSC supported /
		bool has_btsc; /*< true if BTSC supported /
		bool has_smatx; /*< true if mat_tx is available /
		bool has_smarx; /*< true if mat_rx is available /
		bool has_gpio; /*< true if GPIO is available /
		bool has_irqn; /*< true if IRQN is available /
		bool has_lna; /< true if LNA (aka PGA) present /
		bool has_oob; /< true if OOB supported /
		bool has_ntsc; /< true if NTSC supported /
		bool has_btsc; /< true if BTSC supported /
		bool has_smatx; /< true if mat_tx is available /
		bool has_smarx; /< true if mat_rx is available /
		bool has_gpio; /< true if GPIO is available /
		bool has_irqn; /< true if IRQN is available /
		/* A1/A2/A... */
		u8 mfx; /*< metal fix /
		u8 mfx; /< metal fix /

		/* tuner settings */
		bool mirror_freq_spect_oob;/*< tuner inversion (true = tuner mirrors the signal /
		bool mirror_freq_spect_oob;/< tuner inversion (true = tuner mirrors the signal /

		/* standard/channel settings */
		enum drx_standard standard; /*< current standard information /
		enum drx_standard standard; /< current standard information /
		enum drx_modulation constellation;
		/*< current constellation /
		s32 frequency; /*< center signal frequency in KHz /
		/< current constellation /
		s32 frequency; /< center signal frequency in KHz /
		enum drx_bandwidth curr_bandwidth;
		/*< current channel bandwidth /
		enum drx_mirror mirror; /*< current channel mirror /
		/< current channel bandwidth /
		enum drx_mirror mirror; /< current channel mirror /

		/* signal quality information */
		u32 fec_bits_desired; /*< BER accounting period /
		u16 fec_vd_plen; /*< no of trellis symbols: VD SER measurement period /
		u16 qam_vd_prescale; /*< Viterbi Measurement Prescale /
		u16 qam_vd_period; /*< Viterbi Measurement period /
		u16 fec_rs_plen; /*< defines RS BER measurement period /
		u16 fec_rs_prescale; /*< ReedSolomon Measurement Prescale /
		u16 fec_rs_period; /*< ReedSolomon Measurement period /
		bool reset_pkt_err_acc; /*< Set a flag to reset accumulated packet error /
		u16 pkt_err_acc_start; /*< Set a flag to reset accumulated packet error /
		u32 fec_bits_desired; /< BER accounting period /
		u16 fec_vd_plen; /< no of trellis symbols: VD SER measurement period /
		u16 qam_vd_prescale; /< Viterbi Measurement Prescale /
		u16 qam_vd_period; /< Viterbi Measurement period /
		u16 fec_rs_plen; /< defines RS BER measurement period /
		u16 fec_rs_prescale; /< ReedSolomon Measurement Prescale /
		u16 fec_rs_period; /< ReedSolomon Measurement period /
		bool reset_pkt_err_acc; /< Set a flag to reset accumulated packet error /
		u16 pkt_err_acc_start; /< Set a flag to reset accumulated packet error /

		/* HI configuration */
		u16 hi_cfg_timing_div; /*< HI Configure() parameter 2 /
		u16 hi_cfg_bridge_delay; /*< HI Configure() parameter 3 /
		u16 hi_cfg_wake_up_key; /*< HI Configure() parameter 4 /
		u16 hi_cfg_ctrl; /*< HI Configure() parameter 5 /
		u16 hi_cfg_transmit; /*< HI Configure() parameter 6 /
		u16 hi_cfg_timing_div; /< HI Configure() parameter 2 /
		u16 hi_cfg_bridge_delay; /< HI Configure() parameter 3 /
		u16 hi_cfg_wake_up_key; /< HI Configure() parameter 4 /
		u16 hi_cfg_ctrl; /< HI Configure() parameter 5 /
		u16 hi_cfg_transmit; /< HI Configure() parameter 6 /

		/* UIO configuration */
		enum drxuio_mode uio_sma_rx_mode;/*< current mode of SmaRx pin /
		enum drxuio_mode uio_sma_tx_mode;/*< current mode of SmaTx pin /
		enum drxuio_mode uio_gpio_mode; /*< current mode of ASEL pin /
		enum drxuio_mode uio_irqn_mode; /*< current mode of IRQN pin /
		enum drxuio_mode uio_sma_rx_mode;/< current mode of SmaRx pin /
		enum drxuio_mode uio_sma_tx_mode;/< current mode of SmaTx pin /
		enum drxuio_mode uio_gpio_mode; /< current mode of ASEL pin /
		enum drxuio_mode uio_irqn_mode; /< current mode of IRQN pin /

		/* IQM fs frequecy shift and inversion */
		u32 iqm_fs_rate_ofs; /*< frequency shifter setting after setchannel /
		bool pos_image; /*< Ture: positive image /
		u32 iqm_fs_rate_ofs; /< frequency shifter setting after setchannel /
		bool pos_image; /< Ture: positive image /
		/* IQM RC frequecy shift */
		u32 iqm_rc_rate_ofs; /*< frequency shifter setting after setchannel /
		u32 iqm_rc_rate_ofs; /< frequency shifter setting after setchannel /

		/* ATV configuration */
		u32 atv_cfg_changed_flags; /*< flag: flags cfg changes /
		s16 atv_top_equ0[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU0__A /
		s16 atv_top_equ1[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU1__A /
		s16 atv_top_equ2[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU2__A /
		s16 atv_top_equ3[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU3__A /
		bool phase_correction_bypass;/*< flag: true=bypass /
		s16 atv_top_vid_peak; /*< shadow of ATV_TOP_VID_PEAK__A /
		u16 atv_top_noise_th; /*< shadow of ATV_TOP_NOISE_TH__A /
		bool enable_cvbs_output; /*< flag CVBS ouput enable /
		bool enable_sif_output; /*< flag SIF ouput enable /
		u32 atv_cfg_changed_flags; /< flag: flags cfg changes /
		s16 atv_top_equ0[DRXJ_COEF_IDX_MAX]; /< shadow of ATV_TOP_EQU0__A /
		s16 atv_top_equ1[DRXJ_COEF_IDX_MAX]; /< shadow of ATV_TOP_EQU1__A /
		s16 atv_top_equ2[DRXJ_COEF_IDX_MAX]; /< shadow of ATV_TOP_EQU2__A /
		s16 atv_top_equ3[DRXJ_COEF_IDX_MAX]; /< shadow of ATV_TOP_EQU3__A /
		bool phase_correction_bypass;/< flag: true=bypass /
		s16 atv_top_vid_peak; /< shadow of ATV_TOP_VID_PEAK__A /
		u16 atv_top_noise_th; /< shadow of ATV_TOP_NOISE_TH__A /
		bool enable_cvbs_output; /< flag CVBS ouput enable /
		bool enable_sif_output; /< flag SIF ouput enable /
		enum drxjsif_attenuation sif_attenuation;
		/*< current SIF att setting /
		/< current SIF att setting /
		/* Agc configuration for QAM and VSB */
		struct drxj_cfg_agc qam_rf_agc_cfg; /*< qam RF AGC config /
		struct drxj_cfg_agc qam_if_agc_cfg; /*< qam IF AGC config /
		struct drxj_cfg_agc vsb_rf_agc_cfg; /*< vsb RF AGC config /
		struct drxj_cfg_agc vsb_if_agc_cfg; /*< vsb IF AGC config /
		struct drxj_cfg_agc qam_rf_agc_cfg; /< qam RF AGC config /
		struct drxj_cfg_agc qam_if_agc_cfg; /< qam IF AGC config /
		struct drxj_cfg_agc vsb_rf_agc_cfg; /< vsb RF AGC config /
		struct drxj_cfg_agc vsb_if_agc_cfg; /< vsb IF AGC config /

		/* PGA gain configuration for QAM and VSB */
		u16 qam_pga_cfg; /*< qam PGA config /
		u16 vsb_pga_cfg; /*< vsb PGA config /
		u16 qam_pga_cfg; /< qam PGA config /
		u16 vsb_pga_cfg; /< vsb PGA config /

		/* Pre SAW configuration for QAM and VSB */
		struct drxj_cfg_pre_saw qam_pre_saw_cfg;
		/*< qam pre SAW config /
		/< qam pre SAW config /
		struct drxj_cfg_pre_saw vsb_pre_saw_cfg;
		/*< qam pre SAW config /
		/< qam pre SAW config /

		/* Version information */
		char v_text[2][12]; /*< allocated text versions /
		struct drx_version v_version[2]; /*< allocated versions structs /
		char v_text[2][12]; /< allocated text versions /
		struct drx_version v_version[2]; /< allocated versions structs /
		struct drx_version_list v_list_elements[2];
		/*< allocated version list /
		/< allocated version list /

		/* smart antenna configuration */
		bool smart_ant_inverted;
		@@ -502,25 +502,25 @@ struct drxj_cfg_atv_output {
		bool oob_power_on;

		/* MPEG static bitrate setting */
		u32 mpeg_ts_static_bitrate; /*< bitrate static MPEG output /
		bool disable_te_ihandling; /*< MPEG TS TEI handling /
		bool bit_reverse_mpeg_outout;/*< MPEG output bit order /
		u32 mpeg_ts_static_bitrate; /< bitrate static MPEG output /
		bool disable_te_ihandling; /< MPEG TS TEI handling /
		bool bit_reverse_mpeg_outout;/< MPEG output bit order /
		enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate;
		/*< MPEG output clock rate /
		/< MPEG output clock rate /
		enum drxj_mpeg_start_width mpeg_start_width;
		/*< MPEG Start width /
		/< MPEG Start width /

		/* Pre SAW & Agc configuration for ATV */
		struct drxj_cfg_pre_saw atv_pre_saw_cfg;
		/*< atv pre SAW config /
		struct drxj_cfg_agc atv_rf_agc_cfg; /*< atv RF AGC config /
		struct drxj_cfg_agc atv_if_agc_cfg; /*< atv IF AGC config /
		u16 atv_pga_cfg; /*< atv pga config /
		/< atv pre SAW config /
		struct drxj_cfg_agc atv_rf_agc_cfg; /< atv RF AGC config /
		struct drxj_cfg_agc atv_if_agc_cfg; /< atv IF AGC config /
		u16 atv_pga_cfg; /< atv pga config /

		u32 curr_symbol_rate;

		/* pin-safe mode */
		bool pdr_safe_mode; /*< PDR safe mode activated /
		bool pdr_safe_mode; /< PDR safe mode activated /
		u16 pdr_safe_restore_val_gpio;
		u16 pdr_safe_restore_val_v_sync;
		u16 pdr_safe_restore_val_sma_rx;
		@@ -531,12 +531,12 @@ struct drxj_cfg_atv_output {
		enum drxj_cfg_oob_lo_power oob_lo_pow;

		struct drx_aud_data aud_data;
		/*< audio storage /};
		/< audio storage /};

		/*-------------------------------------------------------------------------
		Access MACROS
		-------------------------------------------------------------------------*/
		/**
		/*
		* \brief Compilable references to attributes
		* \param d pointer to demod instance
		*
		@@ -554,7 +554,7 @@ Access MACROS
		DEFINES
		-------------------------------------------------------------------------*/

		/**
		/*
		* \def DRXJ_NTSC_CARRIER_FREQ_OFFSET
		* \brief Offset from picture carrier to centre frequency in kHz, in RF domain
		*
		@@ -569,7 +569,7 @@ DEFINES
		*/
		#define DRXJ_NTSC_CARRIER_FREQ_OFFSET ((s32)(1750))

		/**
		/*
		* \def DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET
		* \brief Offset from picture carrier to centre frequency in kHz, in RF domain
		*
		@@ -585,7 +585,7 @@ DEFINES
		*/
		#define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET ((s32)(2375))

		/**
		/*
		* \def DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET
		* \brief Offset from picture carrier to centre frequency in kHz, in RF domain
		*
		@@ -601,7 +601,7 @@ DEFINES
		*/
		#define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET ((s32)(2775))

		/**
		/*
		* \def DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET
		* \brief Offset from picture carrier to centre frequency in kHz, in RF domain
		*
		@@ -616,7 +616,7 @@ DEFINES
		*/
		#define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET ((s32)(-3255))

		/**
		/*
		* \def DRXJ_FM_CARRIER_FREQ_OFFSET
		* \brief Offset from sound carrier to centre frequency in kHz, in RF domain
		*

drivers/media/dvb-frontends/drxk.h

+3 −2

Original line number	Diff line number	Diff line
		@@ -20,17 +20,18 @@
		* @antenna_dvbt: GPIO bit for changing antenna to DVB-C. A value of 1
		* means that 1=DVBC, 0 = DVBT. Zero means the opposite.
		* @mpeg_out_clk_strength: DRXK Mpeg output clock drive strength.
		* @chunk_size: maximum size for I2C messages
		* @microcode_name: Name of the firmware file with the microcode
		* @qam_demod_parameter_count: The number of parameters used for the command
		* to set the demodulator parameters. All
		* firmwares are using the 2-parameter commmand.
		* An exception is the "drxk_a3.mc" firmware,
		* An exception is the ``drxk_a3.mc`` firmware,
		* which uses the 4-parameter command.
		* A value of 0 (default) or lower indicates that
		* the correct number of parameters will be
		* automatically detected.
		*
		* On the *_gpio vars, bit 0 is UIO-1, bit 1 is UIO-2 and bit 2 is
		* On the ``*_gpio`` vars, bit 0 is UIO-1, bit 1 is UIO-2 and bit 2 is
		* UIO-3.
		*/
		struct drxk_config {

drivers/media/dvb-frontends/dvb-pll.h

+6 −5

Original line number	Diff line number	Diff line
		@@ -33,11 +33,12 @@
		/**
		* Attach a dvb-pll to the supplied frontend structure.
		*
		* @param fe Frontend to attach to.
		* @param pll_addr i2c address of the PLL (if used).
		* @param i2c i2c adapter to use (set to NULL if not used).
		* @param pll_desc_id dvb_pll_desc to use.
		* @return Frontend pointer on success, NULL on failure
		* @fe: Frontend to attach to.
		* @pll_addr: i2c address of the PLL (if used).
		* @i2c: i2c adapter to use (set to NULL if not used).
		* @pll_desc_id: dvb_pll_desc to use.
		*
		* return: Frontend pointer on success, NULL on failure
		*/
		#if IS_REACHABLE(CONFIG_DVB_PLL)
		extern struct dvb_frontend dvb_pll_attach(struct dvb_frontend fe,